LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TR1_BUFFER8 IS
PORT (Din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);		
EN:IN STD_LOGIC;
           Dout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END TR1_BUFFER8;
ARCHITECTURE four OF TR1_BUFFER8 IS 
	BEGIN 
PROCESS(EN,Din)                                   //定義了一個進程
	BEGIN
IF(EN='1')THEN
	Dout <= Din;
ELSE 
	Dout <="ZZZZZZZZ";                             //Z表示高阻態
		END IF;
END PROCESS;
END four;