LIBRARY IEEE;										//使用標準庫
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHECK IS									//實體定義
    PORT(A:IN STD_LOGIC_VECTOR(7 downto 0);		//端口定義
          Y:OUT STD_LOGIC);
END CHECK;
ARCHITECTURE rtl OF CHECK IS
BEGIN
PROCESS(Al)
    VARIABLE TMP: STD_LOGIC;
    BEGIN
        TMP='0';
        FOR i IN 0 to 7 LOOP							//使用循環結構
            TMP= TMP XOR A(i);
        END LOOP;
    END PROCESS;
END rtl;