/*
MEMORY
{
	PAGE 0:	PROG: 	origin = 0x3000 	len = 0x1000

	PAGE 1:	SPRAM: 	origin = 0x60,  	len = 0x20
		    VAR:	origin = 0x80,		len = 0x680
		    DATA: 	origin = 0x700,    	len = 0x900

	PAGE 2:	DATA:	origin = 0x1000,   	len = 0x2000
}

SECTIONS
{
	.text:	>	PROG 	PAGE 0
	.bss: 	> 	VAR	PAGE 1
	.data: 	> 	DATA 	PAGE 1
}*/

MEMORY
{
	PAGE 0:
	VEC: origin = 1000h, length = 0ffh
	PROG: origin = 1100h, length = 8000h
	PAGE 1:
	DATA: origin = 080h, length = 0807fh
}
SECTIONS
{
	.text > PROG PAGE 0
	.cinit > PROG PAGE 0
	.switch > PROG PAGE 0
	.int_table > VEC PAGE 0
	.data > DATA PAGE 1
	.bss > DATA PAGE 1
	.const > DATA PAGE 1
	.sysmem > DATA PAGE 1
	.stack > DATA PAGE 1
}