-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L77 is GPIOB[9]~59 at LC5
A1L77_or_out = A1L67;
A1L77 = A1L77_or_out;


--A1L58 is GPIOB~62 at LC89
A1L58_p1_out = SW[1] & CPLD_FRNB;
A1L58_or_out = A1L58_p1_out;
A1L58 = A1L58_or_out;


--A1L68 is GPIOB~64 at LC94
A1L68_p1_out = SW[2] & USB_FLAGB;
A1L68_or_out = A1L68_p1_out;
A1L68 = A1L68_or_out;


--A1L78 is GPIOB~66 at LC97
A1L78_p1_out = SW[3] & USB_FLAGC;
A1L78_or_out = A1L78_p1_out;
A1L78 = A1L78_or_out;


--A1L88 is GPIOB~68 at LC91
A1L88_p1_out = SW[4] & USB_RDY;
A1L88_or_out = A1L88_p1_out;
A1L88 = A1L88_or_out;


--A1L19 is INT1~9 at LC8
A1L19_p1_out = SW[4] & USB_INTn;
A1L19_or_out = A1L19_p1_out;
A1L19 = A1L19_or_out;


--A1L84 is DSP_ADDR[5]~50 at LC77
A1L84_or_out = DSP_ADDR[5];
A1L84 = A1L84_or_out;


--A1L741 is SPI_CLK~2 at LC1
A1L741 = SPI_CLK;

--A1L4 is AICCSn$latch~23 at LC1
A1L4_p2_out = !DREG[5] & A1L2;
A1L4_p3_out = A1L2 & !DREG[4];
A1L4_p4_out = A1L2 & !DREG[3];
A1L4 = A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;


--A1L94 is DSP_ADDR[5]~52 at LC53
A1L94_or_out = DSP_ADDR[5];
A1L94 = A1L94_or_out;


--A1L15 is DSP_ADDR[6]~54 at LC52
A1L15_or_out = DSP_ADDR[6];
A1L15 = A1L15_or_out;


--A1L64 is DSP_ADDR[4]~56 at LC76
A1L64_or_out = DSP_ADDR[4];
A1L64 = A1L64_or_out;


--A1L831 is RDn~2 at LC80
A1L831_or_out = RDn;
A1L831 = A1L831_or_out;


--A1L31 is CPLD_LED3~11 at LC51
A1L31_p1_out = !WEn & !CS0AND1n & DSP_ADDR[7];
A1L31_or_out = A1L31_p1_out;
A1L31 = A1L31_or_out;


--A1L271 is WEn~13 at LC75
A1L271_or_out = WEn;
A1L271 = A1L271_or_out;


--A1L151 is SPI_SIMO~6 at LC30
A1L151_or_out = A1L051;
A1L151 = A1L151_or_out;


--A1L361 is USB_CSn~8 at LC44
A1L361_p1_out = WEn & RDn;
A1L361_or_out = DSP_ADDR[7] # A1L361_p1_out # DSP_ADDR[4] # !DSP_ADDR[3] # CS0AND1n;
A1L361 = A1L361_or_out;


--A1L961 is USB_PKTEND~7 at LC43
A1L961_p1_out = DSP_ADDR[4] & !WEn & DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7];
A1L961_or_out = A1L961_p1_out;
A1L961 = !(A1L961_or_out);


--A1L47 is GPIOB[8]~71 at LC4
A1L47_or_out = A1L37;
A1L47 = A1L47_or_out;


--LED[8] is LED[8] at LC20
LED[8]_or_out = A1L96;
LED[8]_reg_input = LED[8]_or_out;
LED[8]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[8] = DFFE(LED[8]_reg_input, GLOBAL(WEn), , , LED[8]_p3_out);


--LED[7] is LED[7] at LC21
LED[7]_or_out = A1L76;
LED[7]_reg_input = LED[7]_or_out;
LED[7]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[7] = DFFE(LED[7]_reg_input, GLOBAL(WEn), , , LED[7]_p3_out);


--LED[6] is LED[6] at LC22
LED[6]_or_out = A1L56;
LED[6]_reg_input = LED[6]_or_out;
LED[6]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[6] = DFFE(LED[6]_reg_input, GLOBAL(WEn), , , LED[6]_p3_out);


--LED[5] is LED[5] at LC24
LED[5]_or_out = A1L36;
LED[5]_reg_input = LED[5]_or_out;
LED[5]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[5] = DFFE(LED[5]_reg_input, GLOBAL(WEn), , , LED[5]_p3_out);


--LED[4] is LED[4] at LC25
LED[4]_or_out = A1L16;
LED[4]_reg_input = LED[4]_or_out;
LED[4]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[4] = DFFE(LED[4]_reg_input, GLOBAL(WEn), , , LED[4]_p3_out);


--LED[3] is LED[3] at LC27
LED[3]_or_out = A1L95;
LED[3]_reg_input = LED[3]_or_out;
LED[3]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[3] = DFFE(LED[3]_reg_input, GLOBAL(WEn), , , LED[3]_p3_out);


--LED[2] is LED[2] at LC28
LED[2]_or_out = A1L75;
LED[2]_reg_input = LED[2]_or_out;
LED[2]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[2] = DFFE(LED[2]_reg_input, GLOBAL(WEn), , , LED[2]_p3_out);


--LED[1] is LED[1] at LC29
LED[1]_or_out = A1L55;
LED[1]_reg_input = LED[1]_or_out;
LED[1]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[1] = DFFE(LED[1]_reg_input, GLOBAL(WEn), , , LED[1]_p3_out);


--DREG[7] is DREG[7] at LC50
DREG[7]_or_out = !A1L96;
DREG[7]_reg_input = DREG[7]_or_out;
DREG[7]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[7] = DFFE(DREG[7]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[7]_p3_out);


--DREG[6] is DREG[6] at LC17
DREG[6]_or_out = !A1L76;
DREG[6]_reg_input = DREG[6]_or_out;
DREG[6]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[6] = DFFE(DREG[6]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[6]_p3_out);


--DREG[5] is DREG[5] at LC19
DREG[5]_or_out = !A1L56;
DREG[5]_reg_input = DREG[5]_or_out;
DREG[5]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[5] = DFFE(DREG[5]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[5]_p3_out);


--DREG[4] is DREG[4] at LC23
DREG[4]_or_out = !A1L36;
DREG[4]_reg_input = DREG[4]_or_out;
DREG[4]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[4] = DFFE(DREG[4]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[4]_p3_out);


--DREG[3] is DREG[3] at LC26
DREG[3]_or_out = !A1L16;
DREG[3]_reg_input = DREG[3]_or_out;
DREG[3]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[3] = DFFE(DREG[3]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[3]_p3_out);


--DREG[2] is DREG[2] at LC31
DREG[2]_or_out = !A1L95;
DREG[2]_reg_input = DREG[2]_or_out;
DREG[2]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[2] = DFFE(DREG[2]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[2]_p3_out);


--DREG[1] is DREG[1] at LC32
DREG[1]_or_out = !A1L75;
DREG[1]_reg_input = DREG[1]_or_out;
DREG[1]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[1] = DFFE(DREG[1]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[1]_p3_out);


--DREG[0] is DREG[0] at LC18
DREG[0]_or_out = !A1L55;
DREG[0]_reg_input = DREG[0]_or_out;
DREG[0]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[0] = DFFE(DREG[0]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[0]_p3_out);


--A1L22 is CPLD_SDA~3 at LC92
A1L22_or_out = A1L12;
A1L22 = A1L22_or_out;


--A1L61 is CPLD_NFCE$latch~10 at LC78
A1L61_p1_out = A1L71 & A1L671;
A1L61_p2_out = A1L61 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L571;
A1L61_p3_out = A1L61 & A1L71;
A1L61_or_out = A1L61_p1_out # A1L61_p2_out # A1L61_p3_out;
A1L61 = A1L61_or_out;


--A1L131 is MY485_CSn$latch~10 at LC85
A1L131_p1_out = A1L371 & A1L871;
A1L131_p2_out = A1L131 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L481;
A1L131_p3_out = A1L131 & A1L371;
A1L131_or_out = A1L131_p1_out # A1L131_p2_out # A1L131_p3_out;
A1L131 = A1L131_or_out;


--A1L721 is LED_CSn$latch~10 at LC84
A1L721_p0_out = A1L771 & !DREG[6];
A1L721_p1_out = SPI_CS & A1L771;
A1L721_p2_out = A1L721 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L381;
A1L721_p3_out = A1L721 & SPI_CS;
A1L721_p4_out = A1L771 & !DREG[7];
A1L721_or_out = A1L821 # A1L721_p0_out # A1L721_p1_out # A1L721_p2_out # A1L721_p3_out # A1L721_p4_out;
A1L721 = A1L721_or_out;


--A1L331 is M_CSn$latch~10 at LC105
A1L331_p0_out = A1L971 & !DREG[6];
A1L331_p1_out = SPI_CS & A1L971;
A1L331_p2_out = A1L331 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L581;
A1L331_p3_out = A1L331 & SPI_CS;
A1L331_p4_out = A1L971 & !DREG[7];
A1L331_or_out = A1L431 # A1L331_p0_out # A1L331_p1_out # A1L331_p2_out # A1L331_p3_out # A1L331_p4_out;
A1L331 = A1L331_or_out;


--A1L72 is DAFSn$latch~10 at LC72
A1L72_p0_out = A1L081 & !DREG[6];
A1L72_p1_out = SPI_CS & A1L081;
A1L72_p2_out = A1L72 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L681;
A1L72_p3_out = A1L72 & SPI_CS;
A1L72_p4_out = A1L081 & !DREG[7];
A1L72_or_out = A1L82 # A1L72_p0_out # A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = A1L72_or_out;


--A1L241 is SDSPI_CSn$latch~10 at LC67
A1L241_p0_out = A1L181 & !DREG[6];
A1L241_p1_out = SPI_CS & A1L181;
A1L241_p2_out = A1L241 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L781;
A1L241_p3_out = A1L241 & SPI_CS;
A1L241_p4_out = A1L181 & !DREG[7];
A1L241_or_out = A1L341 # A1L241_p0_out # A1L241_p1_out # A1L241_p2_out # A1L241_p3_out # A1L241_p4_out;
A1L241 = A1L241_or_out;


--A1L2 is AICCSn$latch~10 at LC3
A1L2_p0_out = A1L281 & !DREG[6];
A1L2_p1_out = SPI_CS & A1L281;
A1L2_p2_out = A1L2 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L881;
A1L2_p3_out = A1L2 & SPI_CS;
A1L2_p4_out = A1L281 & !DREG[7];
A1L2_or_out = A1L3 # A1L2_p0_out # A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = A1L2_or_out;


--~GND~0 is ~GND~0 at LC9
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1 at LC11
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~VCC~0 is ~VCC~0 at LC56
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1 at LC57
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~VCC~2 is ~VCC~2 at LC59
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);


--~VCC~3 is ~VCC~3 at LC60
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);


--~VCC~4 is ~VCC~4 at LC61
~VCC~4_or_out = GND;
~VCC~4 = !(~VCC~4_or_out);


--~VCC~5 is ~VCC~5 at LC62
~VCC~5_or_out = GND;
~VCC~5 = !(~VCC~5_or_out);


--~VCC~6 is ~VCC~6 at LC64
~VCC~6_or_out = GND;
~VCC~6 = !(~VCC~6_or_out);


--~VCC~7 is ~VCC~7 at LC33
~VCC~7_or_out = GND;
~VCC~7 = !(~VCC~7_or_out);


--~VCC~8 is ~VCC~8 at LC86
~VCC~8_or_out = GND;
~VCC~8 = !(~VCC~8_or_out);


--~VCC~9 is ~VCC~9 at LC93
~VCC~9_or_out = GND;
~VCC~9 = !(~VCC~9_or_out);


--~GND~2 is ~GND~2 at LC49
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3 at LC108
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~VCC~10 is ~VCC~10 at LC88
~VCC~10_or_out = GND;
~VCC~10 = !(~VCC~10_or_out);


--~VCC~11 is ~VCC~11 at LC100
~VCC~11_or_out = GND;
~VCC~11 = !(~VCC~11_or_out);


--~VCC~12 is ~VCC~12 at LC102
~VCC~12_or_out = GND;
~VCC~12 = !(~VCC~12_or_out);


--~VCC~13 is ~VCC~13 at LC54
~VCC~13_or_out = GND;
~VCC~13 = !(~VCC~13_or_out);


--~VCC~14 is ~VCC~14 at LC110
~VCC~14_or_out = GND;
~VCC~14 = !(~VCC~14_or_out);


--~VCC~15 is ~VCC~15 at LC113
~VCC~15_or_out = GND;
~VCC~15 = !(~VCC~15_or_out);


--~VCC~16 is ~VCC~16 at LC115
~VCC~16_or_out = GND;
~VCC~16 = !(~VCC~16_or_out);


--~VCC~17 is ~VCC~17 at LC116
~VCC~17_or_out = GND;
~VCC~17 = !(~VCC~17_or_out);


--~VCC~18 is ~VCC~18 at LC117
~VCC~18_or_out = GND;
~VCC~18 = !(~VCC~18_or_out);


--~VCC~19 is ~VCC~19 at LC118
~VCC~19_or_out = GND;
~VCC~19 = !(~VCC~19_or_out);


--~VCC~20 is ~VCC~20 at LC120
~VCC~20_or_out = GND;
~VCC~20 = !(~VCC~20_or_out);


--~VCC~21 is ~VCC~21 at LC121
~VCC~21_or_out = GND;
~VCC~21 = !(~VCC~21_or_out);


--~VCC~22 is ~VCC~22 at LC124
~VCC~22_or_out = GND;
~VCC~22 = !(~VCC~22_or_out);


--~VCC~23 is ~VCC~23 at LC125
~VCC~23_or_out = GND;
~VCC~23 = !(~VCC~23_or_out);


--~VCC~24 is ~VCC~24 at LC126
~VCC~24_or_out = GND;
~VCC~24 = !(~VCC~24_or_out);


--~VCC~25 is ~VCC~25 at LC128
~VCC~25_or_out = GND;
~VCC~25 = !(~VCC~25_or_out);


--~VCC~26 is ~VCC~26 at LC16
~VCC~26_or_out = GND;
~VCC~26 = !(~VCC~26_or_out);


--~VCC~27 is ~VCC~27 at LC14
~VCC~27_or_out = GND;
~VCC~27 = !(~VCC~27_or_out);


--A1L371 is reduce_nor~50sexp at SEXP85
A1L371 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3]);


--A1L471 is reduce_nor~54sexp at SEXP77
A1L471 = EXP(!DREG[0] & !DREG[2] & !DREG[1]);


--A1L71 is CPLD_NFCE~9sexp at SEXP78
A1L71 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L471);


--A1L571 is reduce_nor~56sexp at SEXP80
A1L571 = EXP(!DREG[2] & !DREG[1]);


--A1L671 is reduce_or~528sexp at SEXP68
A1L671 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L571);


--A1L381 is reduce_or~537sexp at SEXP89
A1L381 = EXP(DREG[0] & DREG[2] & DREG[1]);


--A1L771 is reduce_or~529sexp at SEXP88
A1L771 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L381);


--A1L481 is reduce_or~541sexp at SEXP86
A1L481 = EXP(!DREG[0] & DREG[2] & DREG[1]);


--A1L871 is reduce_or~530sexp at SEXP82
A1L871 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L481);


--A1L581 is reduce_or~545sexp at SEXP100
A1L581 = EXP(DREG[0] & DREG[2] & !DREG[1]);


--A1L971 is reduce_or~531sexp at SEXP97
A1L971 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L581);


--A1L681 is reduce_or~549sexp at SEXP65
A1L681 = EXP(!DREG[0] & DREG[2] & !DREG[1]);


--A1L081 is reduce_or~532sexp at SEXP70
A1L081 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L681);


--A1L781 is reduce_or~553sexp at SEXP75
A1L781 = EXP(DREG[0] & !DREG[2] & DREG[1]);


--A1L181 is reduce_or~533sexp at SEXP76
A1L181 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L781);


--A1L881 is reduce_or~557sexp at SEXP1
A1L881 = EXP(!DREG[0] & !DREG[2] & DREG[1]);


--A1L281 is reduce_or~534sexp at SEXP4
A1L281 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L881);


--A1L821 is LED_CSn$latch~22 at LC83
A1L821_p0_out = A1L721 & !DREG[6];
A1L821_p1_out = !DREG[5] & A1L771;
A1L821_p2_out = A1L771 & !DREG[4];
A1L821_p3_out = A1L771 & !DREG[3];
A1L821_p4_out = !DREG[7] & A1L721;
A1L821 = A1L921 # A1L821_p0_out # A1L821_p1_out # A1L821_p2_out # A1L821_p3_out # A1L821_p4_out;


--A1L921 is LED_CSn$latch~23 at LC82
A1L921_p1_out = !DREG[5] & A1L721;
A1L921_p2_out = A1L721 & !DREG[4];
A1L921_p3_out = A1L721 & !DREG[3];
A1L921 = A1L921_p1_out # A1L921_p2_out # A1L921_p3_out;


--A1L431 is M_CSn$latch~22 at LC104
A1L431_p0_out = A1L331 & !DREG[6];
A1L431_p1_out = !DREG[5] & A1L971;
A1L431_p2_out = A1L971 & !DREG[4];
A1L431_p3_out = A1L971 & !DREG[3];
A1L431_p4_out = !DREG[7] & A1L331;
A1L431 = A1L531 # A1L431_p0_out # A1L431_p1_out # A1L431_p2_out # A1L431_p3_out # A1L431_p4_out;


--A1L531 is M_CSn$latch~23 at LC103
A1L531_p1_out = !DREG[5] & A1L331;
A1L531_p2_out = A1L331 & !DREG[4];
A1L531_p3_out = A1L331 & !DREG[3];
A1L531 = A1L531_p1_out # A1L531_p2_out # A1L531_p3_out;


--A1L82 is DAFSn$latch~22 at LC71
A1L82_p0_out = A1L72 & !DREG[6];
A1L82_p1_out = !DREG[5] & A1L081;
A1L82_p2_out = A1L081 & !DREG[4];
A1L82_p3_out = A1L081 & !DREG[3];
A1L82_p4_out = !DREG[7] & A1L72;
A1L82 = A1L92 # A1L82_p0_out # A1L82_p1_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;


--A1L92 is DAFSn$latch~23 at LC70
A1L92_p1_out = !DREG[5] & A1L72;
A1L92_p2_out = A1L72 & !DREG[4];
A1L92_p3_out = A1L72 & !DREG[3];
A1L92 = A1L92_p1_out # A1L92_p2_out # A1L92_p3_out;


--A1L341 is SDSPI_CSn$latch~22 at LC66
A1L341_p0_out = A1L241 & !DREG[6];
A1L341_p1_out = !DREG[5] & A1L181;
A1L341_p2_out = A1L181 & !DREG[4];
A1L341_p3_out = A1L181 & !DREG[3];
A1L341_p4_out = !DREG[7] & A1L241;
A1L341 = A1L441 # A1L341_p0_out # A1L341_p1_out # A1L341_p2_out # A1L341_p3_out # A1L341_p4_out;


--A1L441 is SDSPI_CSn$latch~23 at LC65
A1L441_p1_out = !DREG[5] & A1L241;
A1L441_p2_out = A1L241 & !DREG[4];
A1L441_p3_out = A1L241 & !DREG[3];
A1L441 = A1L441_p1_out # A1L441_p2_out # A1L441_p3_out;


--A1L3 is AICCSn$latch~22 at LC2
A1L3_p0_out = A1L2 & !DREG[6];
A1L3_p1_out = !DREG[5] & A1L281;
A1L3_p2_out = A1L281 & !DREG[4];
A1L3_p3_out = A1L281 & !DREG[3];
A1L3_p4_out = !DREG[7] & A1L2;
A1L3 = A1L4 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;


--DSP_RSTn is DSP_RSTn at PIN_133
--operation mode is input

DSP_RSTn = INPUT();


--DSPCLK_OUT is DSPCLK_OUT at PIN_125
--operation mode is input

DSPCLK_OUT = INPUT();


--R_Wn is R_Wn at PIN_127
--operation mode is input

R_Wn = INPUT();


--RDn is RDn at PIN_126
--operation mode is input

RDn = INPUT();


--WEn is WEn at PIN_128
--operation mode is input

WEn = INPUT();


--READY is READY at PIN_134
--operation mode is input

READY = INPUT();