|MYDSP2812
DSP_RSTn => always1~0.IN0
DSPCLK_OUT => ~NO_FANOUT~
R_Wn => ~NO_FANOUT~
RDn => USB_CSn~0.IN0
RDn => CPLD_RDn.DATAIN
WEn => DREG[7].CLK
WEn => DREG[6].CLK
WEn => DREG[5].CLK
WEn => DREG[4].CLK
WEn => DREG[3].CLK
WEn => DREG[2].CLK
WEn => DREG[1].CLK
WEn => DREG[0].CLK
WEn => LED[8].CLK
WEn => LED[7].CLK
WEn => LED[6].CLK
WEn => LED[5].CLK
WEn => LED[4].CLK
WEn => LED[3].CLK
WEn => LED[2].CLK
WEn => LED[1].CLK
WEn => USB_PKTEND~2.IN1
WEn => USB_CSn~0.IN1
WEn => CPLD_LED2~1.IN1
WEn => CPLD_WEn.DATAIN
READY => ~NO_FANOUT~
NMI <= <GND>
INT1 <= INT1~0.DB_MAX_OUTPUT_PORT_TYPE
INT2 <= <GND>
DSP_ADDR[1] => Equal1.IN13
DSP_ADDR[1] => Equal0.IN13
DSP_ADDR[2] => Equal1.IN12
DSP_ADDR[2] => Equal0.IN12
DSP_ADDR[3] => USB_PKTEND~0.IN1
DSP_ADDR[3] => USB_CSn~2.IN1
DSP_ADDR[3] => Equal1.IN11
DSP_ADDR[3] => Equal0.IN11
DSP_ADDR[4] => USB_PKTEND~0.IN0
DSP_ADDR[4] => USB_CSn~1.IN0
DSP_ADDR[4] => Equal1.IN10
DSP_ADDR[4] => Equal0.IN10
DSP_ADDR[4] => CPLD_LED4.DATAIN
DSP_ADDR[5] => Equal1.IN9
DSP_ADDR[5] => Equal0.IN9
DSP_ADDR[5] => CPLD_LED1.DATAIN
DSP_ADDR[6] => Equal1.IN8
DSP_ADDR[6] => Equal0.IN8
DSP_ADDR[6] => CPLD_LED3.DATAIN
DSP_ADDR[7] => USB_PKTEND~3.IN1
DSP_ADDR[7] => USB_CSn~5.IN1
DSP_ADDR[7] => Equal1.IN7
DSP_ADDR[7] => Equal0.IN7
DSP_ADDR[7] => CPLD_LED2~0.IN0
GPIOB[10] <= comb~0
GPIOB[11] <= comb~1
GPIOB[12] <= comb~2
GPIOB[13] <= comb~3
GPIOB[14] <= GPIOB~12
CS0AND1n => USB_PKTEND~4.IN1
CS0AND1n => USB_CSn~6.IN1
CS0AND1n => always1~1.IN0
CS0AND1n => CPLD_LED2~2.IN1
SPI_CS => Selector12.IN5
SPI_CS => Selector8.IN5
SPI_CS => Selector6.IN5
SPI_CS => Selector4.IN5
SPI_CS => Selector2.IN5
SPI_CLK => CPLDSPI_CLK.DATAIN
SPI_SOMI <= <UNC>
LD[1] <= LED[1].DB_MAX_OUTPUT_PORT_TYPE
LD[2] <= LED[2].DB_MAX_OUTPUT_PORT_TYPE
LD[3] <= LED[3].DB_MAX_OUTPUT_PORT_TYPE
LD[4] <= LED[4].DB_MAX_OUTPUT_PORT_TYPE
LD[5] <= LED[5].DB_MAX_OUTPUT_PORT_TYPE
LD[6] <= LED[6].DB_MAX_OUTPUT_PORT_TYPE
LD[7] <= LED[7].DB_MAX_OUTPUT_PORT_TYPE
LD[8] <= LED[8].DB_MAX_OUTPUT_PORT_TYPE
SW[1] => GPIOB~8.IN0
SW[2] => GPIOB~9.IN0
SW[3] => GPIOB~10.IN0
SW[4] => INT1~0.IN0
SW[4] => GPIOB~11.IN0
CPLD_SCL <= CPLD_SCL~0.DB_MAX_OUTPUT_PORT_TYPE
CPLD_SDA <= CPLD_SDA~0
CPLDSPI_CLK <= SPI_CLK.DB_MAX_OUTPUT_PORT_TYPE
CPLDSPI_SIMO <= CPLDSPI_SIMO~0
USB_CSn <= USB_CSn~6.DB_MAX_OUTPUT_PORT_TYPE
USB_PKTEND <= USB_PKTEND~4.DB_MAX_OUTPUT_PORT_TYPE
USB_INTn => INT1~0.IN1
USB_RDY => GPIOB~11.IN1
USB_FLAGA => ~NO_FANOUT~
USB_FLAGB => GPIOB~9.IN1
USB_FLAGC => GPIOB~10.IN1
IFCLK <= <UNC>
CPLD_LED1 <= DSP_ADDR[5].DB_MAX_OUTPUT_PORT_TYPE
CPLD_LED2 <= CPLD_LED2~2.DB_MAX_OUTPUT_PORT_TYPE
CPLD_LED3 <= DSP_ADDR[6].DB_MAX_OUTPUT_PORT_TYPE
CPLD_LED4 <= DSP_ADDR[4].DB_MAX_OUTPUT_PORT_TYPE
CPLD_WEn <= WEn.DB_MAX_OUTPUT_PORT_TYPE
CPLD_FALE <= <VCC>
CPLD_FCLE <= <VCC>
CPLD_NFCE <= CPLD_NFCE$latch.DB_MAX_OUTPUT_PORT_TYPE
CPLD_RDn <= RDn.DB_MAX_OUTPUT_PORT_TYPE
CPLD_FRNB => GPIOB~8.IN1
LED_CSn <= LED_CSn$latch.DB_MAX_OUTPUT_PORT_TYPE
MY485_CSn <= MY485_CSn$latch.DB_MAX_OUTPUT_PORT_TYPE
M_CSn <= M_CSn$latch.DB_MAX_OUTPUT_PORT_TYPE
DACSn <= <GND>
DAFSn <= DAFSn$latch.DB_MAX_OUTPUT_PORT_TYPE
SDSPI_CSn <= SDSPI_CSn$latch.DB_MAX_OUTPUT_PORT_TYPE
AICCSn <= AICCSn$latch.DB_MAX_OUTPUT_PORT_TYPE
IOPORT[1] <= <UNC>
IOPORT[2] <= <UNC>
IOPORT[3] <= <UNC>
IOPORT[4] <= <UNC>
IOPORT[5] <= <UNC>
IOPORT[6] <= <UNC>
IOPORT[7] <= <UNC>
IOPORT[8] <= <UNC>
IOPORT[9] <= <UNC>
IOPORT[10] <= <UNC>
IOPORT[11] <= <UNC>
IOPORT[12] <= <UNC>
IOPORT[13] <= <UNC>
IOPORT[14] <= <UNC>