?? prev_cmp_mydsp2812.tan.qmsg
字號:
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "MY485_CSn\$latch~10 " "Warning: Node \"MY485_CSn\$latch~10\"" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "CPLD_NFCE\$latch~10 " "Warning: Node \"CPLD_NFCE\$latch~10\"" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "WEn " "Info: Assuming node \"WEn\" is an undefined clock" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 64 -1 0 } } { "d:/altera72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera72/quartus/bin/Assignment Editor.qase" 1 { { 0 "WEn" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WEn " "Info: No valid register-to-register data paths exist for clock \"WEn\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DREG\[7\] DSP_DATA\[7\] WEn 6.700 ns register " "Info: tsu for register \"DREG\[7\]\" (data pin = \"DSP_DATA\[7\]\", clock pin = \"WEn\") is 6.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest pin register " "Info: + Longest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DSP_DATA\[7\] 1 PIN PIN_32 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_32; Fanout = 1; PIN Node = 'DSP_DATA\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_DATA[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns DSP_DATA\[7\]~0 2 COMB IO33 2 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = IO33; Fanout = 2; COMB Node = 'DSP_DATA\[7\]~0'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { DSP_DATA[7] DSP_DATA[7]~0 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 69 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 7.200 ns DREG\[7\] 3 REG LC50 48 " "Info: 3: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { DSP_DATA[7]~0 DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 62.50 % ) " "Info: Total cell delay = 4.500 ns ( 62.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 37.50 % ) " "Info: Total interconnect delay = 2.700 ns ( 37.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { DSP_DATA[7] DSP_DATA[7]~0 DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { DSP_DATA[7] {} DSP_DATA[7]~0 {} DREG[7] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WEn destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"WEn\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns WEn 1 CLK PIN_128 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_128; Fanout = 20; CLK Node = 'WEn'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { WEn } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns DREG\[7\] 2 REG LC50 48 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { WEn DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { DSP_DATA[7] DSP_DATA[7]~0 DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "7.200 ns" { DSP_DATA[7] {} DSP_DATA[7]~0 {} DREG[7] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } "" } } { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "WEn AICCSn DREG\[7\] 17.700 ns register " "Info: tco from clock \"WEn\" to destination pin \"AICCSn\" through register \"DREG\[7\]\" is 17.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WEn source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"WEn\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns WEn 1 CLK PIN_128 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_128; Fanout = 20; CLK Node = 'WEn'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { WEn } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns DREG\[7\] 2 REG LC50 48 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { WEn DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.700 ns + Longest register pin " "Info: + Longest register to pin delay is 12.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DREG\[7\] 1 REG LC50 48 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.800 ns) 6.700 ns WideOr8~122 2 COMB SEXP8 4 " "Info: 2: + IC(2.900 ns) + CELL(3.800 ns) = 6.700 ns; Loc. = SEXP8; Fanout = 4; COMB Node = 'WideOr8~122'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { DREG[7] WideOr8~122 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 190 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 11.100 ns AICCSn\$latch~10 3 COMB LOOP LC3 5 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 11.100 ns; Loc. = LC3; Fanout = 5; COMB LOOP Node = 'AICCSn\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "AICCSn\$latch~10 LC3 " "Info: Loc. = LC3; Node \"AICCSn\$latch~10\"" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AICCSn$latch~10 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AICCSn$latch~10 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { WideOr8~122 AICCSn$latch~10 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 12.700 ns AICCSn 4 PIN PIN_142 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 12.700 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'AICCSn'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { AICCSn$latch~10 AICCSn } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 113 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.800 ns ( 77.17 % ) " "Info: Total cell delay = 9.800 ns ( 77.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 22.83 % ) " "Info: Total interconnect delay = 2.900 ns ( 22.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "12.700 ns" { DREG[7] WideOr8~122 AICCSn$latch~10 AICCSn } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "12.700 ns" { DREG[7] {} WideOr8~122 {} AICCSn$latch~10 {} AICCSn {} } { 0.000ns 2.900ns 0.000ns 0.000ns } { 0.000ns 3.800ns 4.400ns 1.600ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "12.700 ns" { DREG[7] WideOr8~122 AICCSn$latch~10 AICCSn } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "12.700 ns" { DREG[7] {} WideOr8~122 {} AICCSn$latch~10 {} AICCSn {} } { 0.000ns 2.900ns 0.000ns 0.000ns } { 0.000ns 3.800ns 4.400ns 1.600ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SPI_CS AICCSn 14.000 ns Longest " "Info: Longest tpd from source pin \"SPI_CS\" to destination pin \"AICCSn\" is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns SPI_CS 1 PIN PIN_97 5 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_97; Fanout = 5; PIN Node = 'SPI_CS'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_CS } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.800 ns) 8.000 ns Selector2~9sexpand1 2 COMB SEXP4 3 " "Info: 2: + IC(2.800 ns) + CELL(3.800 ns) = 8.000 ns; Loc. = SEXP4; Fanout = 3; COMB Node = 'Selector2~9sexpand1'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { SPI_CS Selector2~9sexpand1 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 190 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 12.400 ns AICCSn\$latch~10 3 COMB LOOP LC3 5 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 12.400 ns; Loc. = LC3; Fanout = 5; COMB LOOP Node = 'AICCSn\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "AICCSn\$latch~10 LC3 " "Info: Loc. = LC3; Node \"AICCSn\$latch~10\"" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AICCSn$latch~10 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AICCSn$latch~10 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { Selector2~9sexpand1 AICCSn$latch~10 } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 14.000 ns AICCSn 4 PIN PIN_142 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 14.000 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'AICCSn'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { AICCSn$latch~10 AICCSn } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 113 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns ( 80.00 % ) " "Info: Total cell delay = 11.200 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "14.000 ns" { SPI_CS Selector2~9sexpand1 AICCSn$latch~10 AICCSn } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "14.000 ns" { SPI_CS {} SPI_CS~out {} Selector2~9sexpand1 {} AICCSn$latch~10 {} AICCSn {} } { 0.000ns 0.000ns 2.800ns 0.000ns 0.000ns } { 0.000ns 1.400ns 3.800ns 4.400ns 1.600ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DREG\[7\] DSP_ADDR\[2\] WEn -0.700 ns register " "Info: th for register \"DREG\[7\]\" (data pin = \"DSP_ADDR\[2\]\", clock pin = \"WEn\") is -0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WEn destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"WEn\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns WEn 1 CLK PIN_128 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_128; Fanout = 20; CLK Node = 'WEn'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { WEn } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns DREG\[7\] 2 REG LC50 48 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { WEn DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns DSP_ADDR\[2\] 1 PIN PIN_61 16 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_61; Fanout = 16; PIN Node = 'DSP_ADDR\[2\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_ADDR[2] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.300 ns) 5.400 ns DREG\[7\] 2 REG LC50 48 " "Info: 2: + IC(2.700 ns) + CELL(1.300 ns) = 5.400 ns; Loc. = LC50; Fanout = 48; REG Node = 'DREG\[7\]'" { } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { DSP_ADDR[2] DREG[7] } "NODE_NAME" } } { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 176 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.700 ns ( 50.00 % ) " "Info: Total cell delay = 2.700 ns ( 50.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 50.00 % ) " "Info: Total interconnect delay = 2.700 ns ( 50.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { DSP_ADDR[2] DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "5.400 ns" { DSP_ADDR[2] {} DSP_ADDR[2]~out {} DREG[7] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 1.300ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { WEn DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { WEn {} WEn~out {} DREG[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } { "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera72/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { DSP_ADDR[2] DREG[7] } "NODE_NAME" } } { "d:/altera72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera72/quartus/bin/Technology_Viewer.qrui" "5.400 ns" { DSP_ADDR[2] {} DSP_ADDR[2]~out {} DREG[7] {} } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 1.300ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 15 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 13:18:56 2008 " "Info: Processing ended: Wed Apr 23 13:18:56 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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