library ieee;
use ieee.std_logic_1164.all;
use ieee.std_Logic_unsigned.all;

entity frediv is
generic(n:integer range 0 to  50:=2);
port(clk:in std_logic;
     clkout:out std_logic);
end;

architecture bb of frediv is
signal counter:integer range 0 to 10;
signal tmpclk:std_logic;
begin
   process(clk)
    begin
      if rising_edge(clk) then
         if counter=n then
           tmpclk<=not tmpclk;
           counter<=0;
         else
             counter<=counter+1;
         end if;
      end if;
  end process;
clkout<=tmpclk;
end;