library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sin_out is
  port(clk:in std_logic;
       data_convert:in std_logic;
       rom:in std_logic_vector(7 downto 0);
       data_out:out std_logic_vector(7 downto 0));
end sin_out;

architecture beha of sin_out is
begin
 process(clk)
  begin
  if rising_edge(clk) then 
   if data_convert='1' then
     data_out<=not rom;
   else data_out<=rom;
   end if;
  end if;
 end process;
end;