library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_pcw is
port(clr,clk:in std_logic;
     pcw:in std_logic_vector(7 downto 0);--控制相位字,每次按鍵下降沿,相位字自加1
     data_in:in std_logic_vector(9 downto 0);
     address:out std_logic_vector(9 downto 0));
end add_pcw;

architecture add of add_pcw is
begin
    process(clk,clr)
    begin
    if clr='0' then
      address<=(others=>'0');
    elsif rising_edge(clk) then
        address<=data_in+pcw;
    end if;
     end process;
end add;