LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX16 IS PORT (
						a,b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
						Y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
						MUL,EQUAL	:IN STD_LOGIC
);END MUX16;
ARCHITECTURE arch OF MUX16 IS
BEGIN
	PROCESS(MUL,EQUAL)
BEGIN
	IF MUL='1'AND EQUAL='1'THEN
y(15 DOWNTO 0) <= a(15 DOWNTO 0)*B(15 DOWNTO 0);
END IF;
END PROCESS;
END ARCH;