?? reg.rpt
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Project Information e:\cal\reg.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/27/2007 11:49:41
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
reg EP1K100QC208-3 6 16 0 0 0 % 16 0 %
User Pins: 6 16 0
Project Information e:\cal\reg.rpt
** FILE HIERARCHY **
|reg4:11|
|reg4:11|reg1:1|
|reg4:11|reg1:2|
|reg4:11|reg1:3|
|reg4:11|reg1:4|
|4to1:10|
|4to1:9|
|4to1:8|
|4to1:7|
|1to4:6|
Device-Specific Information: e:\cal\reg.rpt
reg
***** Logic for device 'reg' compiled without errors.
Device: EP1K100QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R O O O R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E U U U E E E E E E E E E E E E E E E E E E E E
S S S S S S V S S S S S S S S S S S S S V T T T S S S S S S S S S S S S S S S S S S S S
E E E E E E C E E E E E E V E E E E E E E C C C C E E V E E E E E E E E E E E V E E E E E E E
R R R R R R C R R R R R R C R R R R R R R C O O O R R C R R R R R R R R R R R C R R R R R R R
V V V V V V I V V V V V V C V V V V V G V V I D D D G V V C V V V V V V G V V V V V C V V V V V V V
E E E E C E E N E E E E E E I E E E E E N E E N E E E N E E I E E E E E E N E E E E E I E E C E E E E E
D D D D 0 D D T D D D D D D O D D D D D D D D T 2 3 1 D D D O D D D D D D D D D D D D O D D 1 D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
A0 | 11 146 | VCCIO
D0 | 12 145 | GND
B0 | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
C3 | 16 141 | RESERVED
B3 | 17 140 | RESERVED
A3 | 18 139 | RESERVED
D3 | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K100QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | A1
RESERVED | 31 126 | D1
GND | 32 125 | B1
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
D2 | 36 121 | RESERVED
RESERVED | 37 120 | A2
RESERVED | 38 119 | B2
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R R G V C I O G G R V R R C R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E E N C L N U N N E C E E 2 E E E C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C R C T D D S C S S S S S C S S S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E E I L C E I E E E E E I E E E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R R N K O R O R R R R R N R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V V T D V V V V V V T V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D 0 D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\cal\reg.rpt
reg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B49 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 1/26( 3%)
D31 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 1/26( 3%)
F14 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 1/26( 3%)
H21 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 1/26( 3%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 16/141 ( 11%)
Total logic cells used: 16/4992 ( 0%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 16/19968 ( 0%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 16
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
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