OUTCODE0 : INPUT;
OUTCODE1 : INPUT;
OUTCODE2 : INPUT;
OUTCODE3 : INPUT;

-- Node name is 'AIN0' 
-- Equation name is 'AIN0', type is output 
AIN0     =  _LC7_D7;

-- Node name is 'AIN1' 
-- Equation name is 'AIN1', type is output 
AIN1     =  _LC3_B32;

-- Node name is 'AIN2' 
-- Equation name is 'AIN2', type is output 
AIN2     =  _LC5_I51;

-- Node name is 'AIN3' 
-- Equation name is 'AIN3', type is output 
AIN3     =  _LC5_L33;

-- Node name is 'BIN0' 
-- Equation name is 'BIN0', type is output 
BIN0     =  _LC1_D7;

-- Node name is 'BIN1' 
-- Equation name is 'BIN1', type is output 
BIN1     =  _LC1_B32;

-- Node name is 'BIN2' 
-- Equation name is 'BIN2', type is output 
BIN2     =  _LC2_I51;

-- Node name is 'BIN3' 
-- Equation name is 'BIN3', type is output 
BIN3     =  _LC3_L33;

-- Node name is 'CIN0' 
-- Equation name is 'CIN0', type is output 
CIN0     =  _LC5_D7;

-- Node name is 'CIN1' 
-- Equation name is 'CIN1', type is output 
CIN1     =  _LC6_B32;

-- Node name is 'CIN2' 
-- Equation name is 'CIN2', type is output 
CIN2     =  _LC1_I51;

-- Node name is 'CIN3' 
-- Equation name is 'CIN3', type is output 
CIN3     =  _LC8_L33;

-- Node name is 'DIN0' 
-- Equation name is 'DIN0', type is output 
DIN0     =  _LC2_D7;

-- Node name is 'DIN1' 
-- Equation name is 'DIN1', type is output 
DIN1     =  _LC8_B32;

-- Node name is 'DIN2' 
-- Equation name is 'DIN2', type is output 
DIN2     =  _LC3_I51;

-- Node name is 'DIN3' 
-- Equation name is 'DIN3', type is output 
DIN3     =  _LC1_L33;

-- Node name is '|reg1:1|:1' = '|reg1:1|Q0' 
-- Equation name is '_LC7_D7', type is buried 
_LC7_D7  = DFFE( OUTCODE0, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:1|:3' = '|reg1:1|Q1' 
-- Equation name is '_LC3_B32', type is buried 
_LC3_B32 = DFFE( OUTCODE1, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:1|:4' = '|reg1:1|Q2' 
-- Equation name is '_LC5_I51', type is buried 
_LC5_I51 = DFFE( OUTCODE2, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:1|:5' = '|reg1:1|Q3' 
-- Equation name is '_LC5_L33', type is buried 
_LC5_L33 = DFFE( OUTCODE3, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:2|:1' = '|reg1:2|Q0' 
-- Equation name is '_LC1_D7', type is buried 
_LC1_D7  = DFFE( _LC7_D7, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:2|:3' = '|reg1:2|Q1' 
-- Equation name is '_LC1_B32', type is buried 
_LC1_B32 = DFFE( _LC3_B32, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:2|:4' = '|reg1:2|Q2' 
-- Equation name is '_LC2_I51', type is buried 
_LC2_I51 = DFFE( _LC5_I51, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:2|:5' = '|reg1:2|Q3' 
-- Equation name is '_LC3_L33', type is buried 
_LC3_L33 = DFFE( _LC5_L33, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:3|:1' = '|reg1:3|Q0' 
-- Equation name is '_LC5_D7', type is buried 
_LC5_D7  = DFFE( _LC1_D7, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:3|:3' = '|reg1:3|Q1' 
-- Equation name is '_LC6_B32', type is buried 
_LC6_B32 = DFFE( _LC1_B32, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:3|:4' = '|reg1:3|Q2' 
-- Equation name is '_LC1_I51', type is buried 
_LC1_I51 = DFFE( _LC2_I51, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:3|:5' = '|reg1:3|Q3' 
-- Equation name is '_LC8_L33', type is buried 
_LC8_L33 = DFFE( _LC3_L33, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:4|:1' = '|reg1:4|Q0' 
-- Equation name is '_LC2_D7', type is buried 
_LC2_D7  = DFFE( _LC5_D7, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:4|:3' = '|reg1:4|Q1' 
-- Equation name is '_LC8_B32', type is buried 
_LC8_B32 = DFFE( _LC6_B32, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:4|:4' = '|reg1:4|Q2' 
-- Equation name is '_LC3_I51', type is buried 
_LC3_I51 = DFFE( _LC1_I51, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|reg1:4|:5' = '|reg1:4|Q3' 
-- Equation name is '_LC1_L33', type is buried 
_LC1_L33 = DFFE( _LC8_L33, GLOBAL( INCLK), GLOBAL( CLR),  VCC,  VCC);



Project Information                                            e:\cal\reg4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 56,194K