?? 4to1.rpt
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EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\4to1.rpt
4to1
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
-- Node name is 'b0~1' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b0~1', location is LC4_A1, type is buried.
-- synthesized logic cell
_LC4_A1 = LCELL( a0);
-- Node name is 'b0' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b0', type is output
b0 = _LC4_A1;
-- Node name is 'b1~1' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b1~1', location is LC8_I34, type is buried.
-- synthesized logic cell
_LC8_I34 = LCELL( a1);
-- Node name is 'b1' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b1', type is output
b1 = _LC8_I34;
-- Node name is 'b2~1' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b2~1', location is LC8_B21, type is buried.
-- synthesized logic cell
_LC8_B21 = LCELL( a2);
-- Node name is 'b2' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b2', type is output
b2 = _LC8_B21;
-- Node name is 'b3~1' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b3~1', location is LC7_E25, type is buried.
-- synthesized logic cell
_LC7_E25 = LCELL( a3);
-- Node name is 'b3' from file "4to1.tdf" line 7, column 2
-- Equation name is 'b3', type is output
b3 = _LC7_E25;
Project Information e:\cal\4to1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 55,663K
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