when TxCMD =>        if tx_bit_cnt < x"7" then          next_state <= TxCMD;        else          case cmd is            when WREN | WRDI | BE | DP => next_state <= CLR_CMD;            when SE | PP | RES | RDCMD | F_RD|WRSR|RDSR => next_state <= WAIT1;            when others => next_state <= CLR_CMD;          end case;        end if;      when WAIT1 =>        case cmd is          when WREN | WRDI | BE | DP => next_state <= CLR_CMD;          when SE | PP | RES | RDCMD | F_RD => next_state <= TxADD_H;          when WRSR => next_state <= TxDATA;          when RDSR => next_state <= RxDATA;          when others => next_state <= CLR_CMD;        end case;      when TxADD_H =>        if tx_bit_cnt < x"7" then          next_state <= TxADD_H;        else          next_state <= WAIT2;        end if;      when WAIT2 => next_state <= TxADD_M;      when TxADD_M =>        if tx_bit_cnt < x"7" then          next_state <= TxADD_M;        else          next_state <= WAIT3;        end if;      when WAIT3 => next_state <= TxADD_L;      when TxADD_L =>        if tx_bit_cnt < x"7" then          next_state <= TxADD_L;        else          case cmd is            when PP => next_state <= WAIT6;            when SE | RES | RDCMD | F_RD => next_state <= WAIT4;            when others => next_state <= CLR_CMD;          end case;        end if;      when WAIT4 =>        case cmd is          when F_RD => next_state <= TxDUMMY;          when RES | RDCMD => next_state <= RxDATA;          when others => next_state <= CLR_CMD;        end case;      when TxDUMMY =>        if tx_bit_cnt < x"7" then          next_state <= TxDUMMY;        else          next_state <= WAIT8;        end if;      when WAIT7 => next_state <= WAIT8;      when WAIT8 =>        case cmd is          when RDCMD | F_RD =>            if rx_empty = '1' then              next_state <= RxDATA;            else              next_state <= WAIT8;            end if;          when others => next_state <= CLR_CMD;        end case;      when RxDATA =>        if rx_bit_cnt < x"7" then          next_state <= RxDATA;        else          case cmd is            when RDCMD | F_RD => next_state <= WAIT7;            when RDSR | RES => next_state <= WAIT5;            when others => next_state <= CLR_CMD;          end case;        end if;      when TxDATA =>        if tx_bit_cnt < x"7" then          next_state <= TxDATA;        else          case cmd is            when PP => next_state <= WAIT6;            when others => next_state <= CLR_CMD;          end case;        end if;      when WAIT6 =>        case cmd is          when PP =>            if tx_new_data = '1' then              next_state <= TxDATA;            else              next_state <= WAIT6;            end if;          when others => next_state <= CLR_CMD;        end case;      when WAIT5 => next_state <= CLR_CMD;      when CLR_CMD => next_state <= IDLE;    end case;  end process;  -- state machine output table  process (state, cmd, tx_data, add_m, add_l, add_h)  begin    -- default values    tx_enable <= '0';    rx_enable <= '0';    rx_bit_cnt_clr <= '1';    tx_reg <= x"FF";    spi_cs_int <= '0';    busy <= '1';    cmd_clr <= '0';    is_tx_data <= '0';    is_wait6 <= '0';    case state is      when IDLE =>        busy <= '0';      when TxCMD =>        tx_reg <= cmd;        tx_enable <= '1';        spi_cs_int <= '1';      when TxDATA =>        tx_reg <= tx_data;        tx_enable <= '1';        spi_cs_int <= '1';        is_tx_data <= '1';      when TxADD_H =>        tx_reg <= add_h;        tx_enable <= '1';        spi_cs_int <= '1';      when TxADD_M =>        tx_reg <= add_m;        tx_enable <= '1';        spi_cs_int <= '1';      when TxADD_L =>        tx_reg <= add_l;        tx_enable <= '1';        spi_cs_int <= '1';      when TxDUMMY =>        tx_reg <= x"00";        tx_enable <= '1';        spi_cs_int <= '1';      when RxDATA =>        rx_bit_cnt_clr <= '0';        rx_enable <= '1';        spi_cs_int <= '1';      when WAIT1 | WAIT2 | WAIT3 | WAIT4 | WAIT8 =>        spi_cs_int <= '1';      when WAIT6 =>        is_wait6 <= '1';        spi_cs_int <= '1';      when WAIT5 | WAIT7 =>        rx_bit_cnt_clr <= '0';        spi_cs_int <= '1';      when CLR_CMD =>        cmd_clr <= '1';      when others => null;    end case;  end process;  -- the tx_empty flip flop  process (rst, wr_data, clk_in)  begin    if rst = '1' then      tx_empty <= '1';    elsif wr_data = '1' then      tx_empty <= '0';    elsif rising_edge (clk_in) then      if tx_empty_set = '1' then        tx_empty <= '1';      end if;    end if;  end process;  -- delay the tx_enable signal  process (rst, clk_in)  begin    if rst = '1' then      tx_enable_d <= '0';    elsif rising_edge (clk_in) then      tx_enable_d <= tx_enable;    end if;  end process;  -- transmitter shift register and bit counter  process (rst, tx_reg, tx_enable_d, clk_in)  begin    if rst = '1' then      tx_sreg <= x"FF";      tx_bit_cnt <= x"0";      tx_empty_set <= '0';    elsif tx_enable_d = '0' then      tx_sreg <= tx_reg;      tx_bit_cnt <= x"0";      tx_empty_set <= '0';    elsif rising_edge (clk_in) then      if clk_en = '1' then        tx_bit_cnt <= tx_bit_cnt + 1;        tx_sreg <= tx_sreg (6 downto 0) & '1';        if tx_bit_cnt = x"6" and is_tx_data = '1' then          tx_empty_set <= '1';        else          tx_empty_set <= '0';        end if;      end if;    end if;  end process;  -- synchronize rd_data  process (rst, clk_in)  begin    if rst = '1' then      rd_data1 <= '0';    elsif falling_edge (clk_in) then      rd_data1 <= rd_data;    end if;  end process;  process (rst, clk_in)  begin    if rst = '1' then      rd_data2 <= '0';    elsif falling_edge (clk_in) then      if rd_data = '0' then        rd_data2 <= rd_data1;      end if;    end if;  end process;  -- the rx_empty flip flop  process (rst, clk_in)  begin    if rst = '1' then      rx_empty <= '1';    elsif rising_edge (clk_in) then      if rx_empty_clr = '1' then        rx_empty <= '0';      elsif rd_data2 = '1' then        rx_empty <= '1';      end if;    end if;  end process;  -- the rx_ready flip flop  process (rst, clk_in)  begin    if rst = '1' then      rx_ready <= '0';    elsif rising_edge (clk_in) then      if rd_data = '1' then        rx_ready <= '0';      elsif rx_ready_set = '1' then        rx_ready <= '1';      end if;    end if;  end process;  -- the rx_data register  process (rst, clk_in)  begin    if rst = '1' then      rx_data <= x"FF";    elsif rising_edge (clk_in) then      if rx_ready_set = '1' then        rx_data <= rx_sreg;      end if;    end if;  end process;  -- receiver shift register and bit counter  process (rst, rx_bit_cnt_clr, clk_in)  begin    if rst = '1' or rx_bit_cnt_clr = '1' then      rx_bit_cnt <= x"0";      rx_ready_set <= '0';      rx_empty_clr <= '0';      rx_sreg <= x"FF";    elsif rising_edge (clk_in) then      if clk_en = '1' then        rx_sreg <= rx_sreg (6 downto 0) & spi_din;        case rx_bit_cnt is          when x"0" =>            rx_bit_cnt <= rx_bit_cnt + 1;            rx_ready_set <= '0';            rx_empty_clr <= '1';          when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>            rx_bit_cnt <= rx_bit_cnt + 1;            rx_ready_set <= '0';            rx_empty_clr <= '0';          when x"7" =>            rx_bit_cnt <= rx_bit_cnt + 1;            rx_ready_set <= '1';            rx_empty_clr <= '0';          when others =>            null;        end case;      end if;    end if;  end process;end rtl;