extern const unsigned char Xthal_cp_num;/* index of highest numbered coprocessor, plus one */extern const unsigned char Xthal_cp_max;/* index of highest allowed coprocessor number, per cfg, plus one *//*extern const unsigned char Xthal_cp_maxcfg;*//* bitmask of which coprocessors are present */extern const unsigned int  Xthal_cp_mask;/* read and write cpenable register */extern void xthal_set_cpenable(unsigned);extern unsigned xthal_get_cpenable(void);/* read & write extra state register *//*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*//*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*//* read & write a TIE coprocessor register *//*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*//*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*//* return coprocessor number based on register *//*extern int xthal_which_cp(unsigned reg);*//*----------------------------------------------------------------------   				Interrupts  ----------------------------------------------------------------------*//* the number of interrupt levels */extern const unsigned char Xthal_num_intlevels;/* the number of interrupts */extern const unsigned char Xthal_num_interrupts;/* mask for level of interrupts */extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];/* mask for level 0 to N interrupts */extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];/* level of each interrupt */extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];/* type per interrupt */extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];/* masks of each type of interrupt */extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];/* interrupt numbers assigned to each timer interrupt */extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];/***  Virtual interrupt prioritization:  ***//*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */extern unsigned	xthal_vpri_to_intlevel(unsigned vpri);extern unsigned	xthal_intlevel_to_vpri(unsigned intlevel);/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */extern unsigned	xthal_int_enable(unsigned);extern unsigned	xthal_int_disable(unsigned);/*  Set/get virtual priority of an interrupt:  */extern int	xthal_set_int_vpri(int intnum, int vpri);extern int	xthal_get_int_vpri(int intnum);/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */extern void	xthal_set_vpri_locklevel(unsigned intlevel);extern unsigned	xthal_get_vpri_locklevel(void);/*  Set/get current virtual interrupt priority:  */extern unsigned	xthal_set_vpri(unsigned vpri);extern unsigned	xthal_get_vpri(unsigned vpri);extern unsigned	xthal_set_vpri_intlevel(unsigned intlevel);extern unsigned	xthal_set_vpri_lock(void);/*----------------------------------------------------------------------   			Generic Interrupt Trampolining Support  ----------------------------------------------------------------------*/typedef void (XtHalVoidFunc)(void);/* *  Bitmask of interrupts currently trampolining down: */extern unsigned Xthal_tram_pending;/* *  Bitmask of which interrupts currently trampolining down *  synchronously are actually enabled; this bitmask is necessary *  because INTENABLE cannot hold that state (sync-trampolining *  interrupts must be kept disabled while trampolining); *  in the current implementation, any bit set here is not set *  in INTENABLE, and vice-versa; once a sync-trampoline is *  handled (at level one), its enable bit must be moved from *  here to INTENABLE: */extern unsigned Xthal_tram_enabled;/* *  Bitmask of interrupts configured for sync trampolining: */extern unsigned Xthal_tram_sync;/*  Trampoline support functions:  */extern unsigned  xthal_tram_pending_to_service( void );extern void      xthal_tram_done( unsigned serviced_mask );extern int       xthal_tram_set_sync( int intnum, int sync );extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );/*  INTENABLE,INTREAD,INTSET,INTCLEAR register access functions:  */extern unsigned  xthal_get_intenable( void );extern void      xthal_set_intenable( unsigned );extern unsigned  xthal_get_intread( void );extern void      xthal_set_intset( unsigned );extern void      xthal_set_intclear( unsigned );/*----------------------------------------------------------------------   				Register Windows  ----------------------------------------------------------------------*//* number of registers in register window */extern const unsigned int  Xthal_num_aregs;extern const unsigned char Xthal_num_aregs_log2;/*  This spill any live register windows (other than the caller's):  */extern void      xthal_window_spill( void );/*----------------------------------------------------------------------   				Cache  ----------------------------------------------------------------------*//* size of the cache lines in log2(bytes) */extern const unsigned char Xthal_icache_linewidth;extern const unsigned char Xthal_dcache_linewidth;/* size of the cache lines in bytes */extern const unsigned short Xthal_icache_linesize;extern const unsigned short Xthal_dcache_linesize;/* number of cache sets in log2(lines per way) */extern const unsigned char Xthal_icache_setwidth;extern const unsigned char Xthal_dcache_setwidth;/* cache set associativity (number of ways) */extern const unsigned int  Xthal_icache_ways;extern const unsigned int  Xthal_dcache_ways;/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */extern const unsigned int  Xthal_icache_size;extern const unsigned int  Xthal_dcache_size;/* cache features */extern const unsigned char Xthal_dcache_is_writeback;extern const unsigned char Xthal_icache_line_lockable;extern const unsigned char Xthal_dcache_line_lockable;/* cache attribute register control (used by other HAL routines) */extern unsigned xthal_get_cacheattr( void );extern unsigned xthal_get_icacheattr( void );extern unsigned xthal_get_dcacheattr( void );extern void     xthal_set_cacheattr( unsigned );extern void     xthal_set_icacheattr( unsigned );extern void     xthal_set_dcacheattr( unsigned );/* initialize cache support (must be called once at startup, before all other cache calls) *//*extern void xthal_cache_startinit( void );*//* reset caches *//*extern void xthal_icache_reset( void );*//*extern void xthal_dcache_reset( void );*//* enable caches */extern void xthal_icache_enable( void );	/* DEPRECATED */extern void xthal_dcache_enable( void );	/* DEPRECATED *//* disable caches */extern void xthal_icache_disable( void );	/* DEPRECATED */extern void xthal_dcache_disable( void );	/* DEPRECATED *//* invalidate the caches */extern void xthal_icache_all_invalidate( void );extern void xthal_dcache_all_invalidate( void );extern void xthal_icache_region_invalidate( void *addr, unsigned size );extern void xthal_dcache_region_invalidate( void *addr, unsigned size );extern void xthal_icache_line_invalidate(void *addr);extern void xthal_dcache_line_invalidate(void *addr);/* write dirty data back */extern void xthal_dcache_all_writeback( void );extern void xthal_dcache_region_writeback( void *addr, unsigned size );extern void xthal_dcache_line_writeback(void *addr);/* write dirty data back and invalidate */extern void xthal_dcache_all_writeback_inv( void );extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );extern void xthal_dcache_line_writeback_inv(void *addr);/* prefetch and lock specified memory range into cache */extern void xthal_icache_region_lock( void *addr, unsigned size );extern void xthal_dcache_region_lock( void *addr, unsigned size );extern void xthal_icache_line_lock(void *addr);extern void xthal_dcache_line_lock(void *addr);/* unlock from cache */extern void xthal_icache_all_unlock( void );extern void xthal_dcache_all_unlock( void );extern void xthal_icache_region_unlock( void *addr, unsigned size );extern void xthal_dcache_region_unlock( void *addr, unsigned size );extern void xthal_icache_line_unlock(void *addr);extern void xthal_dcache_line_unlock(void *addr);/* sync icache and memory */extern void xthal_icache_sync( void );/* sync dcache and memory */extern void xthal_dcache_sync( void );/*----------------------------------------------------------------------   				Debug  ----------------------------------------------------------------------*//*  1 if debug option configured, 0 if not:  */extern const int Xthal_debug_configured;/*  Number of instruction and data break registers:  */extern const int Xthal_num_ibreak;extern const int Xthal_num_dbreak;/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */extern unsigned int xthal_set_soft_break(void *addr);extern void         xthal_remove_soft_break(void *addr, unsigned int);/*----------------------------------------------------------------------   				Disassembler  ----------------------------------------------------------------------*//*  Max expected size of the return buffer for a disassembled instruction (hint only):  */#define XTHAL_DISASM_BUFSIZE	80/*  Disassembly option bits for selecting what to return:  */#define XTHAL_DISASM_OPT_ADDR	0x0001	/* display address */#define XTHAL_DISASM_OPT_OPHEX	0x0002	/* display opcode bytes in hex */#define XTHAL_DISASM_OPT_OPCODE	0x0004	/* display opcode name (mnemonic) */#define XTHAL_DISASM_OPT_PARMS	0x0008	/* display parameters */#define XTHAL_DISASM_OPT_ALL	0x0FFF	/* display everything *//* routine to get a string for the disassembled instruction */extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,		       char *buffer, unsigned buflen, unsigned options );/* routine to get the size of the next instruction. Returns 0 for   illegal instruction */extern int xthal_disassemble_size( unsigned char *instr_buf );/*----------------------------------------------------------------------   				Core Counter  ----------------------------------------------------------------------*//* counter info */extern const unsigned char Xthal_have_ccount;	/* set if CCOUNT register present */extern const unsigned char Xthal_num_ccompare;	/* number of CCOMPAREn registers *//* get CCOUNT register (if not present return 0) */extern unsigned xthal_get_ccount(void);/* set and get CCOMPAREn registers (if not present, get returns 0) */extern void     xthal_set_ccompare(int, unsigned);extern unsigned xthal_get_ccompare(int);/*----------------------------------------------------------------------			Instruction/Data RAM/ROM Access  ----------------------------------------------------------------------*/extern void* xthal_memcpy(void *dst, const void *src, unsigned len);extern void* xthal_bcopy(const void *src, void *dst, unsigned len);/*----------------------------------------------------------------------                           MP Synchronization  ----------------------------------------------------------------------*/extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );extern unsigned xthal_get_prid( void );