/*extern const char  Xthal_have_s32c1i;*/extern const unsigned char Xthal_have_prid;/*----------------------------------------------------------------------                             Miscellaneous  ----------------------------------------------------------------------*/extern const unsigned int  Xthal_release_major;extern const unsigned int  Xthal_release_minor;extern const char * const  Xthal_release_name;extern const char * const  Xthal_release_internal;extern const unsigned char Xthal_memory_order;extern const unsigned char Xthal_have_windowed;extern const unsigned char Xthal_have_density;extern const unsigned char Xthal_have_booleans;extern const unsigned char Xthal_have_loops;extern const unsigned char Xthal_have_nsa;extern const unsigned char Xthal_have_minmax;extern const unsigned char Xthal_have_sext;extern const unsigned char Xthal_have_clamps;extern const unsigned char Xthal_have_mac16;extern const unsigned char Xthal_have_mul16;extern const unsigned char Xthal_have_fp;extern const unsigned char Xthal_have_speculation;extern const unsigned char Xthal_have_exceptions;extern const unsigned char Xthal_xea_version;extern const unsigned char Xthal_have_interrupts;extern const unsigned char Xthal_have_highlevel_interrupts;extern const unsigned char Xthal_have_nmi;extern const unsigned short Xthal_num_writebuffer_entries;extern const unsigned int  Xthal_build_unique_id;/*  Release info for hardware targeted by software upgrades:  */extern const unsigned int  Xthal_hw_configid0;extern const unsigned int  Xthal_hw_configid1;extern const unsigned int  Xthal_hw_release_major;extern const unsigned int  Xthal_hw_release_minor;extern const char * const  Xthal_hw_release_name;extern const char * const  Xthal_hw_release_internal;/*  Internal memories...  */extern const unsigned char Xthal_num_instrom;extern const unsigned char Xthal_num_instram;extern const unsigned char Xthal_num_datarom;extern const unsigned char Xthal_num_dataram;extern const unsigned char Xthal_num_xlmi;extern const unsigned int  Xthal_instrom_vaddr[1];extern const unsigned int  Xthal_instrom_paddr[1];extern const unsigned int  Xthal_instrom_size [1];extern const unsigned int  Xthal_instram_vaddr[1];extern const unsigned int  Xthal_instram_paddr[1];extern const unsigned int  Xthal_instram_size [1];extern const unsigned int  Xthal_datarom_vaddr[1];extern const unsigned int  Xthal_datarom_paddr[1];extern const unsigned int  Xthal_datarom_size [1];extern const unsigned int  Xthal_dataram_vaddr[1];extern const unsigned int  Xthal_dataram_paddr[1];extern const unsigned int  Xthal_dataram_size [1];extern const unsigned int  Xthal_xlmi_vaddr[1];extern const unsigned int  Xthal_xlmi_paddr[1];extern const unsigned int  Xthal_xlmi_size [1];/*----------------------------------------------------------------------                         Memory Management Unit  ----------------------------------------------------------------------*/extern const unsigned char Xthal_have_spanning_way;extern const unsigned char Xthal_have_identity_map;extern const unsigned char Xthal_have_mimic_cacheattr;extern const unsigned char Xthal_have_xlt_cacheattr;extern const unsigned char Xthal_have_cacheattr;extern const unsigned char Xthal_have_tlbs;extern const unsigned char Xthal_mmu_asid_bits;		/* 0 .. 8 */extern const unsigned char Xthal_mmu_asid_kernel;extern const unsigned char Xthal_mmu_rings;		/* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */extern const unsigned char Xthal_mmu_ring_bits;extern const unsigned char Xthal_mmu_sr_bits;extern const unsigned char Xthal_mmu_ca_bits;extern const unsigned int  Xthal_mmu_max_pte_page_size;extern const unsigned int  Xthal_mmu_min_pte_page_size;extern const unsigned char Xthal_itlb_way_bits;extern const unsigned char Xthal_itlb_ways;extern const unsigned char Xthal_itlb_arf_ways;extern const unsigned char Xthal_dtlb_way_bits;extern const unsigned char Xthal_dtlb_ways;extern const unsigned char Xthal_dtlb_arf_ways;/*  Convert between virtual and physical addresses (through static maps only):  *//*** WARNING: these two functions may go away in a future release; don't depend on them! ***/extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );#if 0/*******************   EXPERIMENTAL AND TENTATIVE ONLY   ********************/#define XTHAL_MMU_PAGESZ_COUNT_MAX	8	/* maximum number of different page sizes */extern const char	Xthal_mmu_pagesz_count;		/* 0 .. 8		number of different page sizes configured *//*  Note:  the following table doesn't necessarily have page sizes in increasing order: */extern const char	Xthal_mmu_pagesz_log2[XTHAL_MMU_PAGESZ_COUNT_MAX];	/* 10 .. 28 (0 past count) *//*  Sorted (increasing) table of page sizes, that indexes into the above table: */extern const char	Xthal_mmu_pagesz_sorted[XTHAL_MMU_PAGESZ_COUNT_MAX];	/* 0 .. 7 (0 past count) *//*u32	Xthal_virtual_exceptions;*/	/* bitmask of which exceptions execute in virtual mode... */extern const char	Xthal_mmu_pte_pagesz_log2_min;	/* ?? minimum page size in PTEs */extern const char	Xthal_mmu_pte_pagesz_log2_max;	/* ?? maximum page size in PTEs *//*  Cache Attribute Bits Implemented by the Cache (part of the cache abstraction) */extern const char	Xthal_icache_fca_bits_implemented;	/* ITLB/UTLB only! */extern const char	Xthal_dcache_lca_bits_implemented;	/* DTLB/UTLB only! */extern const char	Xthal_dcache_sca_bits_implemented; 	/* DTLB/UTLB only! *//*  Per TLB Parameters (Instruction, Data, Unified)  */struct XtHalMmuTlb	Xthal_itlb;	/* description of MMU I-TLB generic features */struct XtHalMmuTlb	Xthal_dtlb;	/* description of MMU D-TLB generic features */struct XtHalMmuTlb	Xthal_utlb;	/* description of MMU U-TLB generic features */#define XTHAL_MMU_WAYS_MAX	8	/* maximum number of ways (associativities) for each TLB *//*  Structure for common information described for each possible TLB (instruction, data and unified): */typedef struct XtHalMmuTlb {    u8  	va_bits;		/* 32		(number of virtual address bits) */    u8  	pa_bits;		/* 32		(number of physical address bits) */    bool	tlb_va_indexed;		/* 1	(set if TLB is indexed by virtual address) */    bool	tlb_va_tagged;		/* 0	(set if TLB is tagged by virtual address) */    bool	cache_va_indexed;	/* 1	(set if cache is indexed by virtual address) */    bool	cache_va_tagged;	/* 0	(set if cache is tagged by virtual address) */    /*bool	(whether page tables are traversed in vaddr sorted order, paddr sorted order, ...) */    /*u8	(set of available page attribute bits, other than cache attribute bits defined above) */    /*u32	(various masks for pages, MMU table/TLB entries, etc.) */    u8  	way_count;		/* 0 .. 8	(number of ways, a.k.a. associativities, for this TLB) */    XtHalMmuTlbWay *	ways[XTHAL_MMU_WAYS_MAX];	/* pointers to per-way parms for each way */} XtHalMmuTlb;/*  Per TLB Way (Per Associativity) Parameters  */typedef struct XtHalMmuTlbWay {     u32	index_count_log2;	/* 0 .. 4 */     u32	pagesz_mask;		/* 0 .. 2^pagesz_count - 1	(each bit corresponds to a size */					/*		defined in the Xthal_mmu_pagesz_log2[] table) */     u32	vpn_const_mask;     u32	vpn_const_value;     u64	ppn_const_mask;		/* future may support pa_bits > 32 */     u64	ppn_const_value;     u32	ppn_id_mask;		/* paddr bits taken directly from vaddr */     bool	backgnd_match;		/* 0 or 1 */     /*  These are defined in terms of the XTHAL_CACHE_xxx bits: */     u8 	fca_const_mask;		/* ITLB/UTLB only! */     u8 	fca_const_value;	/* ITLB/UTLB only! */     u8 	lca_const_mask;		/* DTLB/UTLB only! */     u8 	lca_const_value; 	/* DTLB/UTLB only! */     u8 	sca_const_mask; 	/* DTLB/UTLB only! */     u8 	sca_const_value; 	/* DTLB/UTLB only! */     /*  These define an encoding that map 5 bits in TLB and PTE entries to */     /*  8 bits (FCA, ITLB), 16 bits (LCA+SCA, DTLB) or 24 bits (FCA+LCA+SCA, UTLB): */     /*  (they may be moved to struct XtHalMmuTlb) */     u8		ca_bits;		/* number of bits in TLB/PTE entries for cache attributes */     u32 *	ca_map;			/* pointer to array of 2^ca_bits entries of FCA+LCA+SCA bits */} XtHalMmuTlbWay;/* *  The way to determine whether protection support is present in core *  is to [look at Xthal_mmu_rings ???]. *  Give info on memory requirements for MMU tables and other in-memory *  data structures (globally, per task, base and per page, etc.) - whatever bounds can be calculated. *//*  Default vectors:  */xthal_immu_fetch_miss_vectorxthal_dmmu_load_miss_vectorxthal_dmmu_store_miss_vector/*  Functions called when a fault is detected:  */typedef void (XtHalMmuFaultFunc)( unsigned vaddr, ...context... );/*  Or, *//*	a? = vaddr *//*	a? = context... *//*	PS.xxx = xxx */XtHalMMuFaultFunc *Xthal_immu_fetch_fault_func;XtHalMMuFaultFunc *Xthal_dmmu_load_fault_func;XtHalMMuFaultFunc *Xthal_dmmu_store_fault_func;/*  Default Handlers:  *//*  The user and/or kernel exception handlers may jump to these handlers to handle the relevant exceptions, *  according to the value of EXCCAUSE.  The exact register state on entry to these handlers is TBD.  *//*  When multiple TLB entries match (hit) on the same access:  */xthal_immu_fetch_multihit_handlerxthal_dmmu_load_multihit_handlerxthal_dmmu_store_multihit_handler/*  Protection violations according to cache attributes, and other cache attribute mismatches:  */xthal_immu_fetch_attr_handlerxthal_dmmu_load_attr_handlerxthal_dmmu_store_attr_handler/*  Protection violations due to insufficient ring level:  */xthal_immu_fetch_priv_handlerxthal_dmmu_load_priv_handlerxthal_dmmu_store_priv_handler/*  Alignment exception handlers (if supported by the particular Xtensa MMU configuration):  */xthal_dmmu_load_align_handlerxthal_dmmu_store_align_handler/*  Or, alternatively, the OS user and/or kernel exception handlers may simply jump to the *  following entry points which will handle any values of EXCCAUSE not handled by the OS:  */xthal_user_exc_default_handlerxthal_kernel_exc_default_handler#endif /*0*/#ifdef INCLUDE_DEPRECATED_HAL_CODEextern const unsigned char Xthal_have_old_exc_arch;extern const unsigned char Xthal_have_mmu;extern const unsigned int  Xthal_num_regs;extern const unsigned char Xthal_num_iroms;extern const unsigned char Xthal_num_irams;extern const unsigned char Xthal_num_droms;extern const unsigned char Xthal_num_drams;extern const unsigned int  Xthal_configid0;extern const unsigned int  Xthal_configid1;#endif#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE#define XTHAL_24_BIT_BREAK		0x80000000#define XTHAL_16_BIT_BREAK		0x40000000extern const unsigned short	Xthal_ill_inst_16[16];#define XTHAL_DEST_REG		0xf0000000	/* Mask for destination register */#define XTHAL_DEST_REG_INST	0x08000000	/* Branch address is in register */#define XTHAL_DEST_REL_INST	0x04000000	/* Branch address is relative */#define XTHAL_RFW_INST		0x00000800#define XTHAL_RFUE_INST		0x00000400#define XTHAL_RFI_INST		0x00000200#define XTHAL_RFE_INST		0x00000100#define XTHAL_RET_INST		0x00000080#define XTHAL_BREAK_INST	0x00000040#define XTHAL_SYSCALL_INST	0x00000020#define XTHAL_LOOP_END		0x00000010	/* Not set by xthal_inst_type */#define XTHAL_JUMP_INST		0x00000008	/* Call or jump instruction */#define XTHAL_BRANCH_INST	0x00000004	/* Branch instruction */#define XTHAL_24_BIT_INST	0x00000002#define XTHAL_16_BIT_INST   0x00000001typedef struct xthal_state {    unsigned	pc;    unsigned	ar[16];    unsigned	lbeg;    unsigned	lend;    unsigned	lcount;    unsigned	extra_ptr;    unsigned	cpregs_ptr[XTHAL_MAX_CPS];} XTHAL_STATE;extern unsigned int xthal_inst_type(void *addr);extern unsigned int xthal_branch_addr(void *addr);extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */#ifdef __cplusplus}#endif#endif /*!__ASSEMBLY__ */#endif /*XTENSA_HAL_H*/