/********************************************************************************    File Name:  uart.v*      Version:  1.1*         Date:  January 22, 2000*        Model:  Uart Chip* Dependencies:  txmit.v, rcvr.v**      Company:  Xilinx***   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.**                Copyright (c) 2000 Xilinx, Inc.*                All rights reserved*******************************************************************************/`timescale 1ns / 100psmodule uart (rxd,clk1x,rst,sdo,clk1x_enable);                                        //output tbre;                                        //output tsre ;output sdo ;                                        //input [7:0] din ;input rst ;input clk1x ,clk1x_enable;                                        //input wrn ;input rxd ;                                        //input rdn ;                                        //output [7:0] dout ;wire clk16x;                                        //output data_ready ;                                        //output framing_error ;                                        //output parity_error ;wire framing_error,parity_error,data_ready,tsre,rdn,wrn;wire [7:0] din; wire [7:0] dout;  rcvr u1(dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn);txmit u2(din,tsre,rst,clk16x,wrn,sdo);uart_ctr u3(dout,din,clk16x,rst,tsre,wrn,data_ready,framing_error,parity_error,rdn,data);clk_product u4 (clk1x,clk16x,clk1x_enable,rst);endmodulemodule clk_product (clk1x,clk16x,clk1x_enable,rst);  input     clk1x,rst,clk1x_enable;  output    clk16x;  reg clk16x;  reg [10:0] clk1x_div;  initial  begin        clk1x_div =11'd798;       clk16x    =0;           end always @(posedge clk1x  or posedge clk1x_enable)   if (clk1x_enable)       begin        if (clk1x_div==0) clk1x_div =11'd798;        else   begin        clk16x= clk1x_div[10];       clk1x_div = clk1x_div + 1;               end        end       else begin        clk1x_div =11'd798;        clk16x    =0;       endendmodulemodule  uart_ctr(dout,din,clk16x,rst,tsre,wrn,data_ready,framing_error,parity_error,rdn,data);  input[7:0]  dout;  input  data_ready,framing_error,parity_error,tsre,clk16x,rst;  output[7:0]  din;  output[7:0]  data;  output wrn,rdn;    reg wrn,rdn;  reg[7:0] din;  reg[7:0] data;       initial begin                   wrn =1;         rdn =1;           end  always @(posedge clk16x or posedge data_ready )     if ( data_ready )         begin          if( framing_error && parity_error )            begin             rdn =0;            din = 8'hAA;             //ok數據代碼‘AA’            data= dout;            wrn =0;            end else begin             rdn =0;            din = 8'h55;              //錯誤代碼‘55’            data =8'hFF;             wrn =0;            end                                  end else  begin          wrn =1;         rdn =1;          end  endmodule