/********************************************************************************/
/* regs54xx.H	v1.00															*/
/* 版權(quán)(c)	2003-   	北京合眾達(dá)電子技術(shù)有限責(zé)任公司							*/
/* 設(shè)計(jì)者:	段立鋒																*/
/********************************************************************************/

/******************************************************************/
/* Check to see if mmregs.h has been previously included by       */
/* another header, if so, skip this and go on                     */
/******************************************************************/
#if !defined(__54XXREGS)  
#include <limits.h>

/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS                                                            */
/*----------------------------------------------------------------------------*/
#define CONTENTS_OF(addr) \
        (*((volatile unsigned int*)(addr)))

#define LENGTH_TO_BITS(length) \
        (~(0xffffffff << (length)))

/* MACROS to SET, CLEAR and RETURN bits and bitfields in Memory Mapped        */
/* locations using the address of the specified register.                     */

#define REG_READ(addr) \
        (CONTENTS_OF(addr))

#define REG_WRITE(addr,val) \
        (CONTENTS_OF(addr) = (val))

#define MASK_BIT(bit) \
        (1 << (bit))

#define RESET_BIT(addr,bit) \
        (CONTENTS_OF(addr) &= (~MASK_BIT(bit)))

#define GET_BIT(addr,bit) \
        (CONTENTS_OF(addr) & (MASK_BIT(bit)) ? 1 : 0)

#define SET_BIT(addr,bit) \
        (CONTENTS_OF(addr) = (CONTENTS_OF(addr)) | (MASK_BIT(bit)))

#define ASSIGN_BIT_VAL(addr,bit,val) \
        ( (val) ? SET_BIT(addr,bit) : RESET_BIT(addr,bit) )

#define CREATE_FIELD(bit,length) \
        (LENGTH_TO_BITS(length) << (bit))

#define RESET_FIELD(addr,bit,length) \
        ( CONTENTS_OF(addr) &= (~CREATE_FIELD(bit,length)))

#define TRUNCATE(val,bit,length) \
        (((unsigned int)(val) << (bit)) & (CREATE_FIELD(bit, length)))

#define MASK_FIELD(bit,val,length)\
        TRUNCATE(val, bit, length)

#define GET_FIELD(addr,bit,length) \
       ((CONTENTS_OF(addr) & CREATE_FIELD(bit,length)) >> bit)

#define LOAD_FIELD(addr,val,bit,length) \
        (CONTENTS_OF(addr) &= (~CREATE_FIELD(bit,length))\
                               | TRUNCATE(val, bit, length))  


/******************************************************************************/
/* Memory-mapped Byte Manipulation Macros                                     */
/******************************************************************************/
#define CSET_BIT(reg,bit) \
((*((volatile unsigned char *)(reg))) |= (MASK_BIT(bit)))

#define CGET_BIT(reg,bit) \
((*((volatile unsigned char *)(reg))) & (MASK_BIT(bit)) ? 1 : 0)

#define CCLR_BIT(reg,bit) \
((*((volatile unsigned char *)(reg))) &= (~MASK_BIT(bit)))

#define CGET_FIELD(reg,bit,length) \
((*((volatile unsigned char *)(reg)) & (MASK_FIELD(bit,length))) >> bit)

#define CLOAD_FIELD(reg,bit,length,val) \
   ((*((volatile unsigned char *)(reg))) = \
((*((volatile unsigned char *)(reg)) & (~MASK_FIELD(bit,length)))) | (val<<bit))

#define CREG_READ(addr) \
(*((unsigned char *)(addr)))

#define CREG_WRITE(addr,val) \
(*((unsigned char *)(addr)) = (val))

/* MACROS to SET, CLEAR and RETURN bits and bitfields in Memory Mapped        */
/* and Non-Memory Mapped using register names.                                */

#define GET_REG(reg) \
        (reg)

#define SET_REG(reg,val) \
        ((reg)= (val))

#define GET_REG_BIT(reg,bit) \
        ((reg) & MASK_BIT(bit) ? 1 : 0)

#define SET_REG_BIT(reg,bit) \
        ((reg) |= MASK_BIT(bit))

#define RESET_REG_BIT(reg,bit) \
        ((reg) &= (~MASK_BIT(bit)))

#define GET_REG_FIELD(reg,bit,length) \
        (reg & CREATE_FIELD(bit,length)) >> bit)

#define LOAD_REG_FIELD(reg,val,bit,length) \
        (reg &= (~CREATE_FIELD(bit,length)) | (val<<bit))
           
/*****************MCBSP Registers, Bits, Bitfields*****************/
/*-------------------------------------------------------------------*/
/* Define bit fields for Serial Port Control Registers 1 and 2       */
/*-------------------------------------------------------------------*/
#define DLB			15
#define DLB_SZ		 1

#define RJUST		13
#define RJUST_SZ	       2

#define CLKSTP		11
#define CLKSTP_SZ	       2

#define DXENA		 7
#define DXENA_SZ	       1

#define ABIS		 6
#define ABIS_SZ		 1

#define RINTM		 4
#define RINTM_SZ	       2

#define RSYNCERR	       3
#define RSYNCERR_SZ	 1

#define RFULL		 2
#define RFULL_SZ	       1

#define RRDY 		 1
#define RRDY_SZ		 1

#define RRST		 0
#define RRST_SZ		 1

#define FREE		 9
#define FREE_SZ		 1

#define SOFT		 8
#define SOFT_SZ		 1

#define FRST		 7
#define FRST_SZ		 1

#define GRST		 6
#define GRST_SZ		 1

#define XINTM		 4
#define XINTM_SZ	       2

#define XSYNCERR	       3
#define XSYNCERR_SZ	 1

#define XEMPTY		 2
#define XEMPTY_SZ	       1

#define XRDY		 1
#define XRDY_SZ		 1

#define XRST		 0
#define XRST_SZ 	       1

/*-------------------------------------------------------------------*/
/* Define bit fields for Receive Control Registers 1 and 2           */
/*-------------------------------------------------------------------*/
#define RFRLEN1		 8
#define RFRLEN1_SZ	 7

#define RWDLEN1		 5
#define RWDLEN1_SZ	 3

#define RPHASE		15
#define RPHASE_SZ	       1

#define RFRLEN2		 8
#define RFRLEN2_SZ	 7

#define RWDLEN2		 5
#define RWDLEN2_SZ	 3

#define RCOMPAND	       3
#define RCOMPAND_SZ	 2

#define RFIG		 2
#define RFIG_SZ		 1

#define RDATDLY		 0
#define RDATDLY_SZ	 2

/*-------------------------------------------------------------------*/
/* Define bit fields for Transmit Control Registers 1 and 2          */
/*-------------------------------------------------------------------*/
#define XFRLEN1		 8
#define XFRLEN1_SZ	 7

#define XWDLEN1		 5
#define XWDLEN1_SZ	 2

#define XPHASE		15
#define XPHASE_SZ	       1

#define XFRLEN2		 8
#define XFRLEN2_SZ	 7

#define XWDLEN2		 5
#define XWDLEN2_SZ	 3

#define XCOMPAND	       3
#define XCOMPAND_SZ	 2

#define XFIG		 2
#define XFIG_SZ  	       1

#define XDATDLY		 0
#define XDATDLY_SZ       2

/*-------------------------------------------------------------------*/
/* Define bit fields for Sample Rate Generator Registers 1 and 2     */
/*-------------------------------------------------------------------*/
#define FWID		 8
#define FWID_SZ	       8

#define CLKGDV		 0
#define CLKGDV_SZ	       8

#define GSYNC		15
#define GSYNC_SZ	       1

#define CLKSP		14 
#define CLKSP_SZ	       1

#define CLKSM		13 
#define CLKSM_SZ	       1

#define FSGM		12 
#define FSGM_SZ		 1

#define FPER		 0
#define FPER_SZ		12

/*-------------------------------------------------------------------*/
/* Define bit fields for Multi-Channel Control Registers 1 and 2     */
/*-------------------------------------------------------------------*/
#define RPBBLK		 7
#define RPBBLK_SZ	       2

#define RPABLK		 5
#define RPABLK_SZ	       2

#define RCBLK		 2
#define RCBLK_SZ	       3

#define RMCM		 0
#define RMCM_SZ		 1

#define XPBBLK		 7
#define XPBBLK_SZ	       2

#define XPABLK		 5
#define XPABLK_SZ	       2

#define XCBLK		 2
#define XCBLK_SZ	       3

#define XMCM		 0
#define XMCM_SZ		 2

/*-------------------------------------------------------------------*/
/* Define bit fields for Receive Channel Enable Register Partition A */
/*-------------------------------------------------------------------*/
#define RCEA15		15
#define RCEA15_SZ	       1

#define RCEA14		14
#define RCEA14_SZ	       1

#define RCEA13		13 
#define RCEA13_SZ	       1

#define RCEA12		12 
#define RCEA12_SZ	       1
   
#define RCEA11		11 
#define RCEA11_SZ	       1

#define RCEA10		10
#define RCEA10_SZ	       1

#define RCEA9		 9
#define RCEA9_SZ	       1

#define RCEA8		 8
#define RCEA8_SZ	       1

#define RCEA7		 7
#define RCEA7_SZ	       1

#define RCEA6		 6
#define RCEA6_SZ	       1

#define RCEA5		 5
#define RCEA5_SZ	       1

#define RCEA4		 4
#define RCEA4_SZ	       1

#define RCEA3		 3
#define RCEA3_SZ	       1

#define RCEA2		 2
#define RCEA2_SZ	       1

#define RCEA1		 1
#define RCEA1_SZ	       1

#define RCEA0		 0
#define RCEA0_SZ	       1

/*-------------------------------------------------------------------*/
/* Define bit fields for Receive Channel Enable Register Partition B */
/*-------------------------------------------------------------------*/
#define RCEB15		15
#define RCEB15_SZ	       1

#define RCEB14		14
#define RCEB14_SZ	       1

#define RCEB13		13 
#define RCEB13_SZ	       1

#define RCEB12		12 
#define RCEB12_SZ	       1

#define RCEB11		11 
#define RCEB11_SZ	       1

#define RCEB10		10
#define RCEB10_SZ	       1

#define RCEB9		 9
#define RCEB9_SZ	       1

#define RCEB8		 8
#define RCEB8_SZ	       1

#define RCEB7		 7
#define RCEB7_SZ	       1

#define RCEB6		 6
#define RCEB6_SZ	       1

#define RCEB5		 5
#define RCEB5_SZ	       1

#define RCEB4		 4
#define RCEB4_SZ	       1

#define RCEB3		 3
#define RCEB3_SZ	       1

#define RCEB2		 2
#define RCEB2_SZ	       1

#define RCEB1		 1
#define RCEB1_SZ	       1

#define RCEB0		 0
#define RCEB0_SZ	       1

/*-------------------------------------------------------------------*/
/* Define bit fields for Transmit Channel Enable Register Partition A*/
/*-------------------------------------------------------------------*/
#define XCEA15		15
#define XCEA15_SZ	       1