/** @mainpage MCASP CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs
 * for the McASP Module across variousdevices. The CSL developer is expected 
 * to refer to this document while designing APIs for these modules. Some of 
 * the listed APIs may not be applicable to a given McASP Module. While in 
 * other cases this list of APIs may not be sufficient to cover all the features 
 * of a particular McASP Module. The CSL developer should use his discretion in 
 * designing new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *  -#  CSL:  Chip Support Library
 *  -#  API:  Application Programmer Interface
 *  -# MCASP: Application Programmer Interface
 *
 *
 */

/** @file csl_mcasp.h
 *
 * @brief    Header file for functional layer of CSL
 *
 * Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 * Modification 
 *    - modified on: 10/1/2005
 *    - reason: Created the sources
 *
 * 
 * @author asr.
 *
 */
 
#ifndef _CSL_MCASP_H_
#define _CSL_MCASP_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl_error.h>
#include <csl_types.h>
#include <cslr_mcasp.h>
#include <soc.h>

/** @brief McASP0 Tx Buffer Address */
#define MCASP0_TXBUF_ADDR	0x54000000
/** @brief McASP0 Rx Buffer Address */
#define MCASP0_RXBUF_ADDR	0x54000000
/** @brief McASP1 Tx Buffer Address */
#define MCASP1_TXBUF_ADDR	0x55000000
/** @brief McASP1 Rx Buffer Address */
#define MCASP1_RXBUF_ADDR	0x55000000
/** @brief McASP2 Tx Buffer Address */
#define MCASP2_TXBUF_ADDR	0x56000000
/** @brief McASP2 Rx Buffer Address */
#define MCASP2_RXBUF_ADDR	0x56000000

/** 
 * @brief McASP Module specific object structure 
 */
typedef struct CSL_McaspObj {
    /** Pointer to the register overlay structure for the peripheral */
    CSL_McaspRegsOvly   regs;
    /** Specifies a particular instance of McASP */
    Int16               perNo;
    /** Number of serializers */
    Int32               numOfSerializers;
    /** Support for DIT mode */
    Bool                ditStatus;
} CSL_McaspObj;

/** 
 * @brief McASP Module specific Hardware setup global structure 
 */
typedef struct CSL_McaspHwSetupGbl {
    /** Pin function register */
    Uint32  pfunc;
    /** Pin direction register */
    Uint32  pdir;
    /** Global control register - GBLCTL*/
    Uint32  ctl;
    /** Decides whether McASP operates in DIT mode - DITCTL */
    Uint32  ditCtl;
    /** Digital loopback mode setup - DLBEN */
    Uint32  dlbMode;
    /** Mute control register - AMUTE */
    Uint32  amute;
    /** Setup serializer control register (SRCTL0-15) */
    Uint32  serSetup[16];
} CSL_McaspHwSetupGbl;

/** 
 * @brief Hardware setup data clock structure 
 */
typedef struct CSL_McaspHwSetupDataClk {
    /** Clock details ACLK(R/X)CTL */
    Uint32  clkSetupClk;
    /** High clock details AHCLK(R/X)CTL */
    Uint32  clkSetupHiClk;
    /** Configures receive/transmit clock failure detection R/XCLKCHK */
    Uint32  clkChk;
} CSL_McaspHwSetupDataClk;

/** 
* @brief Hardware setup data structure 
*/
typedef struct CSL_McaspHwSetupData {
    /** To mask or not to mask - R/XMASK */
    Uint32                      mask;
    /** Format details as per  - R/XFMT */
    Uint32                      fmt;
    /** Configure the rcv/xmt frame sync - AFSR/XCTL */
    Uint32                      frSyncCtl;
    /** Specifies which TDM slots are active - R/XTDM */
    Uint32                      tdm;
    /** Controls generation of McASP interrupts - R/XINTCTL */
    Uint32                      intCtl;
    /** Status register (controls writable fields of STAT register)-R/XSTAT */
    Uint32                      stat;
    /** Event control register - R/XEVTCTL */
    Uint32                      evtCtl;
    /** Clock settings for rcv/xmt */
    CSL_McaspHwSetupDataClk     clk;
} CSL_McaspHwSetupData;

/** 
 * @brief Hardware setup structure 
 */
typedef struct CSL_McaspHwSetup {
    /** Value to be loaded in global control register (GLBCTL) */
    CSL_McaspHwSetupGbl     glb;
    /** Receiver settings */
    CSL_McaspHwSetupData    rx;
    /** Transmitter settings */
    CSL_McaspHwSetupData    tx;
    /** Power down emulation mode params - PWRDEMU */
    Uint32                  emu;
} CSL_McaspHwSetup;

/**
 * @brief DIT channel/user Left/right data structure
 */ 
typedef enum {
    /** 1st DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_0 = 0,
    /** 2nd DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_1 = 1,
    /** 3rd DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_2 = 2,
    /** 4th DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_3 = 3,
    /** 5th DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_4 = 4,
    /** 6th DIT (channel/user data), (left/right) Register */
    DIT_REGISTER_5 = 5
} CSL_McaspDITRegIndex;

/** 
 * @brief DIT channel status register structure 
 */
typedef struct {
    /** Left channel status registers (DITCSRA0-5) */
    Uint32 chStatusLeft[6];
    /** Right channel status register (DITCSRB0-5) */
    Uint32 chStatusRight[6];
} CSL_McaspChStatusRam;

/** 
 * @brief DIT channel user data register structure 
 */
typedef struct {
    /** Left channel user data registers (DITUDRA0-5) */
    Uint32 userDataLeft[6];
    /** Right channel user data registers (DITUDRB0-5) */
    Uint32 userDataRight[6];
} CSL_McaspUserDataRam;

/**
 * @brief Module specific Configuration structure.This is used to configure McASP
 * instance using CSL_mcaspHwSetupRaw function
 */
typedef struct {
    /** Power down and emulation management register */
    Uint32 PWRDEMU;
    /** Pin function register */
    Uint32 PFUNC;
    /** Pin direction register */
    Uint32 PDIR;
    /** Pin data output register */
    Uint32 PDOUT;
    /** Pin data set register */
    Uint32 PDIN_PDSET;
    /** Pin data clear register */
    Uint32 PDCLR;
    /** Global control register */
    Uint32 GBLCTL;
    /** Audio mute control register */
    Uint32 AMUTE;
    /** Digital loopback control register */
    Uint32 DLBCTL;
    /** DIT mode control register */
    Uint32 DITCTL;
    /** Receive format unit bit mask register */
    Uint32 RMASK;
    /** Receive bit stream format register */
    Uint32 RFMT;
    /** Receive frame sync control register */
    Uint32 AFSRCTL;
    /** Receive clock control register */
    Uint32 ACLKRCTL;
    /** Receive high-frequency clock control register */
    Uint32 AHCLKRCTL;
    /** Receive TDM time slot 0-31 register */
    Uint32 RTDM;
    /** Receiver interrupt control register */
    Uint32 RINTCTL;
    /** Receiver status register */
    Uint32 RSTAT;
    /** Receive clock check control register */
    Uint32 RCLKCHK;
    /** Receiver DMA event control register */
    Uint32 REVTCTL;
    /** Transmit format unit bit mask register */
    Uint32 XMASK;
    /** Transmit bit stream format register */
    Uint32 XFMT;
    /** Transmit frame sync control register */
    Uint32 AFSXCTL;
    /** Transmit clock control register */
    Uint32 ACLKXCTL;
    /** Transmit high-frequency clock control register */
    Uint32 AHCLKXCTL;
    /** Transmit TDM time slot 0-31 register */
    Uint32 XTDM;
    /** Transmitter interrupt control register */
    Uint32 XINTCTL;
    /** Transmitter status register */
    Uint32 XSTAT;
    /** Transmit clock check control register */
    Uint32 XCLKCHK;
    /** Transmitter DMA event control register */
    Uint32 XEVTCTL;
    /** Serializer control register 0 */
    Uint32 SRCTL0;
    /** Serializer control register 1 */
    Uint32 SRCTL1;
    /** Serializer control register 2 */
    Uint32 SRCTL2;
    /** Serializer control register 3 */
    Uint32 SRCTL3;
    /** Serializer control register 4 */
    Uint32 SRCTL4;
    /** Serializer control register 5 */
    Uint32 SRCTL5;
    /** Serializer control register 6 */
    Uint32 SRCTL6;
    /** Serializer control register 7 */
    Uint32 SRCTL7;
    /** Serializer control register 8 */
    Uint32 SRCTL8;
    /** Serializer control register 9 */
    Uint32 SRCTL9;
    /** Serializer control register 10 */
    Uint32 SRCTL10;
    /** Serializer control register 11 */
    Uint32 SRCTL11;
    /** Serializer control register 12 */
    Uint32 SRCTL12;
    /** Serializer control register 13 */
    Uint32 SRCTL13;
    /** Serializer control register 14 */
    Uint32 SRCTL14;
    /** Serializer control register 15 */
    Uint32 SRCTL15;
} CSL_McaspConfig;

/** 
 *  @brief Module specific parameters. Present implementation doesn't have
 *  any module specific parameters.
 */
typedef struct {
    /** 
     *  Bit mask to be used for module specific parameters.
     *  The below declaration is just a place-holder for future
     *  implementation.
     */
    CSL_BitMask32   flags;
} CSL_McaspParam;

/** 
 * @brief Enumeration for the serializer numbers 
 */
typedef enum {
    /** SRCTL0 */
    SERIALIZER_1 = 0,
    /** SRCTL1 */
    SERIALIZER_2 = 1,
    /** SRCTL2 */
    SERIALIZER_3 = 2,
    /** SRCTL3 */
    SERIALIZER_4 = 3,
    /** SRCTL4 */
    SERIALIZER_5 = 4,
    /** SRCTL5 */
    SERIALIZER_6 = 5,
    /** SRCTL5 */
    SERIALIZER_7 = 6,
    /** SRCTL5 */
    SERIALIZER_8 = 7,
    /** SRCTL5 */
    SERIALIZER_9 = 8,
    /** SRCTL5 */
    SERIALIZER_10 = 9,
    /** SRCTL5 */
    SERIALIZER_11 = 10,
    /** SRCTL5 */
    SERIALIZER_12 = 11,
    /** SRCTL5 */
    SERIALIZER_13 = 12,
    /** SRCTL5 */
    SERIALIZER_14 = 13,
    /** SRCTL5 */
    SERIALIZER_15 = 14,
    /** SRCTL5 */
    SERIALIZER_16 = 15
} CSL_McaspSerializerNum;

/** 
 * @brief Enumeration for the serializer mode 
 */
typedef enum {
    /** Serializer is inactive */
    SERIALIZER_INACTIVE = 0,
    /** Serializer is transmitter */
    SERIALIZER_XMT = 1,
    /** Serializer is receiver */
    SERIALIZER_RCV = 2
} CSL_McaspSerMode;

/**
 *  @brief The following stcruture will be used in CSL_MCASP_QUERY_SRCTL_RRDY,
 *  and CSL_MCASP_QUERY_SRCTL_XRDY
 */
typedef struct CSL_McaspSerQuery {
    /** Serializer number */
    CSL_McaspSerializerNum  serNum;
    /** Return value of the query */
    Bool                    serStatus;
} CSL_McaspSerQuery;

/**
 *  @brief The following stcruture will be used in CSL_MCASP_QUERY_SRCTL_SRMOD
 */
typedef struct CSL_McaspSerMmode {
    /** Serializer number */
    CSL_McaspSerializerNum  serNum;
    /** Serializer mode */
    CSL_McaspSerMode        serMode;
} CSL_McaspSerModeQuery;

/**
 *  @brief Enumeration for hardware control commands passed to  @a CSL_mcaspHwControl()
 *
 * This is used to select the commands to control the operations
 * existing setup of McASP. The arguments to be passed with each
 * enumeration if any are specified next to the enumeration. 
 */
typedef enum {
    /**
     * @brief   Configure transmitter global control register  with parameters
     *          passed
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_SET_XMT               = 1,

    /**
     * @brief   Configure receiver global control register  with parameters
     *          passed
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_SET_RCV               = 2,

    /**
     * @brief   Reset transmit frame sync generator
     * @param   (None)
     */
    CSL_MCASP_CMD_RESET_FSYNC_XMT       = 3,

    /**
     * @brief   Reset receive frame sync generator
     * @param   (None)
     */
    CSL_MCASP_CMD_RESET_FSYNC_RCV       = 4,

    /**
     * @brief   Reset all registers
     * @param   (None)
     */
    CSL_MCASP_CMD_REG_RESET             = 5,

    /**
     * @brief   Mute enable
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_AMUTE_ON              = 6,

    /**
     * @brief   Enable digital loopback mode
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_DLB_ON                = 7,

    /**
     * @brief   Configures receive slots
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_CONFIG_RTDM_SLOT     = 8,

    /**
     * @brief   Configures transmit slots
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_CONFIG_XTDM_SLOT     = 9,

    /**
     * @brief   Configures the interrupts on the receive side
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_CONFIG_INTERRUPT_RCV  = 10,

    /**
     * @brief   Configures the interrupts on the transmit side
     * @param   (Uint32 *)
     */
    CSL_MCASP_CMD_CONFIG_INTERRUPT_XMT  = 11,

    /**
     * @brief   Reset clock circuitry for receive
     * @param   (None)
     */
    CSL_MCASP_CMD_CLK_RESET_RCV         = 12,

    /**
     * @brief   Reset clock circuitry for transmit
     * @param   (None)
     */
    CSL_MCASP_CMD_CLK_RESET_XMT         = 13,

    /**
     * @brief   Set receive clock registers with value
     *          (CSL_McaspHwSetupDataClk*) passed
     * @param   (CSL_McaspHwSetupDataClk *)
     */
    CSL_MCASP_CMD_CLK_SET_RCV           = 14,

    /**
     * @brief   Set transmit clock registers with value
     *          (CSL_McaspHwSetupDataClk*) passed
     * @param   (CSL_McaspHwSetupDataClk *)
     */
    CSL_MCASP_CMD_CLK_SET_XMT           = 15,

    /**
     * @brief   Configure the format, frame sync, and other parameters related
     *          to the transmit section