/*****************************************************************************************/
//
// Name: 	BF537 EZ-KIT interface to the AD9866 Mixed-Signal Front-End Evaluation Board 
//
/*****************************************************************************************

Analog Devices, Inc.  All rights reserved.

File Name:			Main.c

Date Modified:			01/19/05	Rev 1.3

Hardware:			BF537 EZ-KIT Board
				BF533/561 Extender Board
				AD9866 Evaluation Board

Hardware Setup:			See readme.txt
						
Purpose:				This code example demonstrates the functionality of a half-duplex
						communication scheme between an ADSP-BF537 Blackfin processor and
						an AD9866 Broadband Modem Mixed-Signal Front-End. The AD9866 has 
						two high-speed converters on board: a 12-bit 80 MSPS ADC and a 12-bit
						200 MSPS DAC. The digitized analog signal from the ADC is read into
						a DMA buffer via the Blackfin's parallel peripheral interface (PPI). 
						Optionally, some processing is performed on the data and it is then 
						transferred out to the DAC via the PPI. A double-buffering scheme 
						is used to boost processing efficiency. 
						
						
						The source code in process.c contains a commented section that performs
						an FFT followed by an inverse FFT on the input data. This acts as a 
						demonstration of how much processing head-room is available. The user may
						replace this section with any appropriate signal processing algorithms 
						as desired. However, it must be ensured that the processing latency for 
						each data buffer half does not exceed the time interval required for 
						its DMA transfer.
						
						A general-purpose timer on the Blackfin processor is used to generate
						periodic interrupts. These interrupts trigger transitions between the
						4 stages of this scheme:
						
						0. RX First Half						1. RX Second Half / Process First Half
 						2. TX First Half / Process Second Half	3. TX Second Half
						
						The timer period was chosen empirically such that it allows enough time 
						for the appropriate DMA transfers to complete. Additionally, some 
						cycles are required for the DMA controller and PPI to change direction.
						
						A more thorough statistical analysis of the latencies associated with
						the PPI/DMA turnaround will be presented in a future application note.
						
******************************************************************************************/

#include "system.h"


EX_EXCEPTION_HANDLER(ex_handler);


// Declare the DMA input and output buffers
section("L1_data_a") volatile short sPPI_RxBuffer[Number_of_ADC_channels * Number_of_Samples * 2];
section("L1_data_b") volatile short sPPI_TxBuffer[(Number_of_DAC_channels * Number_of_Samples * 2)+33];

// GLOBAL scalars

// flag to indicate which half of the output buffer has been transmitted and can be worked on by the user
// i.e. points to the half that DMA is NOT using
short half = 1;			// 0 = first half, 1 = second half

// 2-bit flag indicating which stage of execution is currently under way

short ping_pong = 0;

// semaphore to indicated that a half has been transmitted 
short stage_initialized = 0;

// store IMASK register when interrupts are disabled
int interruptLatch;

// USER CODE

section("L1_code") void main() {
	int i = 0; short temp = 0;
	
// Initialize ports

	temp = *pPORTG_FER;
	ssync();
	temp = 0xFFFF;
	*pPORTG_FER = temp;
	ssync();
	*pPORTG_FER = temp;
	ssync();
	
	temp = *pPORTF_FER;
	ssync();
	temp = 0xFFC0;
	*pPORTF_FER = temp;
	ssync();
	*pPORTF_FER = temp;
	ssync();
	
	temp = *pPORT_MUX;
	ssync();
	temp = 0x0180;
	*pPORT_MUX  = temp;
	ssync();
	*pPORT_MUX  = temp;
	ssync();
	
	// init exception handler
	register_handler(ik_exception,ex_handler);

	// Set CCLK = 594 MHz, SCLK = 118 MHz
	
	
	// Initialize PLL
	
	interruptLatch = cli();
	Set_PLL(22,5);
	sti(interruptLatch);
	
	// Set FFT twiddle factors
	init_twiddle();

    initFlags();

	InitSPI_for_AD9866();
    Init_AD9866();	

	//clear receive buffer
	
	for(i=0; i<Number_of_ADC_channels * Number_of_Samples * 2; i++) {
		sPPI_RxBuffer[i] = 0x7FF0;
	}
	
	// Fill the last 33 words of the TX buffer with midscale values
	// This ensures that the TxDAC interpolation filters are flushed 
	// before the TX path is disabled
	
	for(i= Number_of_ADC_channels * Number_of_Samples * 2; i<((Number_of_ADC_channels * Number_of_Samples * 2)+33); i++) {
		sPPI_TxBuffer[i] = 0x0;
	}
	
	// initialise Hardware


	InitInterrupts();
	
	*pPPI_CONTROL = (short) 0x0000; //Disable PPI
	*pDMA0_CONFIG = 0x0000; // Disable DMA
	*pPPI_CONTROL = (short) 0x387C;	
	*pPPI_DELAY   = 0x1B;
	*pPPI_COUNT   = Number_of_ADC_channels * Number_of_Samples*2;
	*pPPI_FRAME   = 1;
	*pDMA0_CONFIG = 0x6;
	*pDMA0_START_ADDR = (void *) sPPI_RxBuffer;
	*pDMA0_X_MODIFY = Number_of_ADC_channels * Word_Size;
	*pDMA0_X_COUNT = Number_of_Samples*2;		
	*pDMA0_CONFIG = *pDMA0_CONFIG | DMAEN;	// enable DMA  (PPI not enabled yet)
	*pPPI_CONTROL |= PORT_EN;				// enable PPI
	*pPORTFIO_SET = 0x4000;	// RX: Set Flag 14 (RXEN)
	
	initTimer();
	ssync();
	
	// MAIN loop
	// waits indefinetely for timer interrupts.
	// When an interrupt occurs, the appropriate data buffer half is processed.
	// The DMA transfers to and from the data converters are initiated in the
	// ISR which executes before the next iteration of the main loop.
	
	while(1) {

		// sync to interrupt through semaphore
		
		asm("cli %0;" : "=d" (interruptLatch)); asm("ssync;");
		ssync();
		// Check for the semaphore, and process if semaphore indicates completion
		

		if (stage_initialized == 1)  {
			if ((ping_pong == 0) | (ping_pong == 3)) // Correspond to core idle stages
				stage_initialized = 0;	 // reset the semaphore
			else {
				process();	// process appropriate data half
							// and write output to TX buffer
				stage_initialized = 0;  // reset the semaphore
			
			} 		// Inner IF
		} 		// Outer IF
		ssync();
		asm("sti %0;" : : "d" (interruptLatch)); asm("ssync;");
	}			// WHILE

}			// MAIN


int initFlags() {
	// Configure the flags 0-15 as inputs, exceptPF14, PF4, PF3 and PF2
	*pPORTFIO_DIR = *pPORTFIO_DIR & 0x401C;
	*pPORTFIO_DIR = *pPORTFIO_DIR | 0x401C;
	
	// Deassert the output flags
  	*pPORTFIO_CLEAR = 0x401C;
	asm("ssync;");
	return 0;
}



/********************************************************************************/
/***** Init_AD9866()														*****/
/***** Configures the MxFE via the SPI interface							*****/
/***** For further details on this section, consult the AD9866 data sheet   *****/
/********************************************************************************/
void Init_AD9866(void)
{ unsigned char temp =0;	 

	// Low Drive Strength, IAMP disabled
	temp = Write_Byte_to_AD9866(0xE, 0x81);
	// Interpolation Factor = 4, DAC data format = straight binary
	temp = Write_Byte_to_AD9866(0xC, 0x0);		
	// Disable CLKOUT divide-by-two
	temp = Write_Byte_to_AD9866(0x6, 0x00);	
	// Set DAC Power-Down Delay to 0 cycles, disable half-duplex power savings mode
	temp = Write_Byte_to_AD9866(0x3,0x4);
	// Set PLL x4 multiplication for DAC Clock
	temp = Write_Byte_to_AD9866(0x4,0x2);
	 
	// Interpolation Factor = 4, DAC data format = 2's complement
	// NOTE:  Uncomment the following line if executing the demonstrational FFT processing.
	 temp = Write_Byte_to_AD9866(0xC, 0x81);	
}



/* Exception handler */
EX_EXCEPTION_HANDLER(ex_handler)
{
	while(1);
}