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ADSP-BF561 EZ-KIT 

ADC and DAC "TalkThrough" Example

Analog Devices, Inc.
DSP Division
Three Technology Way
Norwood, MA 02062

Date Created:	11/17/03

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This example streams input from a ADC source to a DAC.
An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). 
The frames are then output with a one-frame delay to the DAC (an AD9744 in this example).
In this example, no processing is done on the frames. They are passed unaltered.
This is a dual core project. Please see section IV. to get familiar with the project structure


IMPORTANT NOTE: you do not have to use both the ADC and the DAC. The example can be modified easily to work
				with either one. The coreA project contains all the necessary code for the ADC, the core B
				project contains everything for the DAC.
				Simply comment out in the corresponding main() function what you do not need.
				
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CONTENTS

I.	 FUNCTIONAL DESCRIPTION
II.  HARDWARE SETUP (BEFORE you run the example)		
III. OPERATION DESCRIPTION
IV.  PROJECT STRUCTURE


I.    FUNCTIONAL DESCRIPTION

	Core A sets up Clock frequencies, SDRAM controller and PPI0 to 
	perform the 16bit samples acquisition. Frames are stored in SDRAM (in a circular fashion,
	4 blocks at a time).
	
	Core B sets up PPI1 to perform output of samples to the DAC. It then waits for the first valid frame in memory
	from Core A, and starts the transfers. GP output mode is used.

	The example has been tested on a 
		- AD9244 ADC. This is a 14-bit / 65MSamples/Sec converter
		- AD9744 DAC. This is a 14-bit / up to 165MSamples/Sec converter

II. HARDWARE SETUP	

	a) Required Hardware
		-ADSP-BF561 EZ-kit 
		-ADSP-BF533/561 Extender Card
		-AD9244 Evaluation Board (or equivalent)
		-AD9744 Evaluation Board (or equivalent)
		
	b) DIP switches
           Settings of the switches on the Expander Board:
							SW1 :	1	OFF
									2	ON
									3	OFF
									4	OFF
									5	OFF
									6	OFF

							SW2 :	1	ON
									2	OFF
									3	OFF
									4	ON

							SW3 :	all OFF
							SW4 :	all OFF
														
		   Settings of the switches on the EZ-Kit:
 							SW2 :	all OFF
 							SW5 :	all ON
 							all other switches in default position
		
	c) ADC and DAC clock source:
            there are several ways to provide a clock to the ADC and the DAC.
            Please refer to the documentation for the AD9244 and the AD9744.
            In this example, a 25MHz oscillator was inserted into socket U7 
            of the Expander board and the resulting clock signal on Pin 1 
            (TX_CLK) of connector J3 was brought to the CLKIN SMA connector
            of the AD9244 board. As a result the AD9744 is clocked with the 
            same clock (Pin 33 of J4). With switch SW2 you can select what 
            clocks go to PPI0 clock and PPI1 clock.
            
            IMPORTANT debugging information: with the above ADC and DAC boards,
            you only need to verify that PPI0 gets the ADC clock and PPI1 gets
            the DAC clock. There is no need for framesyncs or other control
            signals. As said, in the above example they are clocked from the
            same source on the extender card. You have other options. Please
            refer to the ADC's and DAC's datasheet. It is assumed here that 
            you are familiar with these boards.
            
	d) ADC clock requirements:
						The ADC and DAC clock frequency must be smaller the SCLK/2
						and the maximum clock for the ADC and DAC device 
						The example sets the SCLK to 120MHz (call to Set_PLL 
						at be beginning of main())

	e) DATA formats:
						The data received over the PPI interfaces is LEFT aligned, 
						signed (1.15 format). The lower bits are to be ignored.
						Make sure that the ADC outputs data in two's complement format.
						On the AD9244 evaluation board, this is achieved by closing JP2.
            
    f) connect the AD9244 board to J3 of the extender card
	g) connect the AD9744 board to J4 of the extender card with a Ribbon Cable.
	   NOTE: if you use a short cable, isolate the ADC board and the DAC board 
	   
	h) Apply Power to all the boards according to the instructions in the datasheets
	   and manuals.
	
	i) Connect a sinusoidal signal to the ADC input. The AD9244 contains a highpass
	   filter, so start with frequencies not below 100kHz
	 
	j) Connect an oscilloscope to the DAC output.


		
III.  OPERATION DESCRIPTION

	- Open the project group "ADC_DAC.dpg" in the VisualDSP Integrated Development
	  Environment (IDDE). Follow instructions in section III.
	  
	- Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP).

	- Run the executables by pressing "multiprocessor run" (CTRL-F5) on the toolbar. DO NOT use the 
	  single core (F5) button. You should see a delayed copy of the ADC input signal on the scope.
	  
	- Halt the processor ("multiprocessor halt" button). If you open a memory window and go to the
	  addresses of _sFrame0,1,2,3, you see the sampled data of the four frames. You may also plot 
	  a graph with the View->Debug Windows->Plot menu command
	  
	- The main header file "system.h" contains #define statements for most of the system settings 
	  (clock frequencies etc) and block sizes.

	  
		
IV. PROJECT STRUCTURE

	This is a dual core project. It consists of a main project - containing only system defines and linker settings-
			".\ADC_DAC.dpj",
	and four sub-projects 		- containing the source code -
			".\coreA\coreA.dpj"					( code exclusive to core A, in L1 memory)
			".\coreB\coreB.dpj"					( code exclusive to core B, in L1 memory)
			".\Shared Memory L2\L2_SRAM.dpj"	( code that is shared between the cores, in on-chip L2 memory)
			".\Shared Memory L3\L3_SDRAM.dpj"	( code that is shared between the cores, in off-chip L3 memory, SDRAM),
	and the project group that ties everything together:
			".\ADC_DAC.dpg"
			
	Follow this procedure to open and compile the project:
	- open the project group (File-> Open-> Project Group)
	- Right click on the main project and re-build the project.