?? main.lis
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GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 1
1 ; ---------------------------------------------------------
2 ; ../src/main.c
3 ; compiled with GCC 2.7.2 ST9+ Software Development Toolchain Version 6.1.3
4 ; Thu Oct 31 15:01:45 2002
5 ;
6 ; OPTIMIZATIONS: 1
7 ; omit-frame-pointer
8 ; OPTIONS: compact
9 ; ---------------------------------------------------------
10
11 gcc_compiled.:
12 .assume no-parmusp,no-fp-on,compact
38
39 .globl MODER
40 .desc MODER, 8bit register
41 MODER= 235
42
43 .globl PLLCONF
44 .desc PLLCONF, 8bit register
45 PLLCONF= 246
46
47 .globl CLK_FLAG
48 .desc CLK_FLAG, 8bit register
49 CLK_FLAG= 242
50
51 .section .text
53
54 .desc clk_init, near
55 .proc clk_init
56 clk_init:
57 .Ltext0:
1:../src/main.c **** #include <cpu.h>
2:../src/main.c **** #include <usb.h>
3:../src/main.c ****
4:../src/main.c **** /*
5:../src/main.c **** ** External Memory mapping
6:../src/main.c **** **
7:../src/main.c **** ** 0 7FFF ROM 32K
8:../src/main.c **** **
9:../src/main.c **** ** DPR2 maps 0x30000 (first 16KB of ROM)
10:../src/main.c **** ** 8000 BFFF ROM
11:../src/main.c **** **
12:../src/main.c **** ** Address latching needs no address wait states
13:../src/main.c **** ** ROM needs 2 data wait states
14:../src/main.c **** */
15:../src/main.c ****
16:../src/main.c **** static void clk_init( void)
17:../src/main.c **** {
59 .LMM2:
18:../src/main.c **** /* CLOCK2 = CLOCK / 1, NO CPUCLK prescaler */
19:../src/main.c **** MODER = 0 ;
61 0000 F5EB00 ld @MODER,#0
62 .LMM3:
20:../src/main.c ****
21:../src/main.c **** /* PLL = CLOCK2 * 6 / 2 */
22:../src/main.c **** spp( RCCU_PG) ;
64 ; #APP
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 2
65 0003 C7DE spp #55
66 ; #NO_APP
67 .LMM4:
23:../src/main.c **** PLLCONF &= 0xD8 ;
69 0005 15F6D8 and @PLLCONF,#216
70 .LMM5:
24:../src/main.c **** PLLCONF |= 0x11 ;
72 0008 05F611 or @PLLCONF,#17
73 .LMM6:
25:../src/main.c ****
26:../src/main.c **** /* Wait until PLL locked */
27:../src/main.c **** while( !( CLK_FLAG & 0x02))
75 .L6:
76 000b A5F202 tm @CLK_FLAG,#2
77 000e 6BFB jxz .L6
78 .LMM7:
28:../src/main.c **** ;
29:../src/main.c ****
30:../src/main.c **** /* Select PLL as INTCLK */
31:../src/main.c **** CLK_FLAG |= 1 ;
80 0010 05F201 or @CLK_FLAG,#1
81 .LMM8:
32:../src/main.c **** }
83 0013 46 ret
84 .endproc
85 .Lscope0:
87
88 .globl P0C0R
89 .desc P0C0R, 8bit register
90 P0C0R= 240
91
92 .globl P0C1R
93 .desc P0C1R, 8bit register
94 P0C1R= 241
95
96 .globl P0C2R
97 .desc P0C2R, 8bit register
98 P0C2R= 242
99
100 .globl P1DR
101 .desc P1DR, 8bit register
102 P1DR= 225
103
104 .globl P1C0R
105 .desc P1C0R, 8bit register
106 P1C0R= 244
107
108 .globl P1C1R
109 .desc P1C1R, 8bit register
110 P1C1R= 245
111
112 .globl P1C2R
113 .desc P1C2R, 8bit register
114 P1C2R= 246
115
116 .globl P3DR
117 .desc P3DR, 8bit register
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 3
118 P3DR= 227
119
120 .globl P3C0R
121 .desc P3C0R, 8bit register
122 P3C0R= 252
123
124 .globl P3C1R
125 .desc P3C1R, 8bit register
126 P3C1R= 253
127
128 .globl P3C2R
129 .desc P3C2R, 8bit register
130 P3C2R= 254
131
132 .globl P4DR
133 .desc P4DR, 8bit register
134 P4DR= 228
135
136 .globl P4C0R
137 .desc P4C0R, 8bit register
138 P4C0R= 240
139
140 .globl P4C1R
141 .desc P4C1R, 8bit register
142 P4C1R= 241
143
144 .globl P4C2R
145 .desc P4C2R, 8bit register
146 P4C2R= 242
147
148 .globl P5DR
149 .desc P5DR, 8bit register
150 P5DR= 229
151
152 .globl P5C0R
153 .desc P5C0R, 8bit register
154 P5C0R= 244
155
156 .globl P5C1R
157 .desc P5C1R, 8bit register
158 P5C1R= 245
159
160 .globl P5C2R
161 .desc P5C2R, 8bit register
162 P5C2R= 246
163
164 .globl P6DR
165 .desc P6DR, 8bit register
166 P6DR= 251
167
168 .globl P6C0R
169 .desc P6C0R, 8bit register
170 P6C0R= 248
171
172 .globl P6C1R
173 .desc P6C1R, 8bit register
174 P6C1R= 249
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 4
175
176 .globl P6C2R
177 .desc P6C2R, 8bit register
178 P6C2R= 250
179
180 .globl DPR2_P
181 .desc DPR2_P, 8bit register
182 DPR2_P= 242
183
184 .globl EMR1
185 .desc EMR1, 8bit register
186 EMR1= 245
187
188 .globl EMR2
189 .desc EMR2, 8bit register
190 EMR2= 246
191
192 .globl WCR
193 .desc WCR, 8bit register
194 WCR= 252
195
196 .globl FAD_CLR
197 .desc FAD_CLR, 8bit register
198 FAD_CLR= 241
200
201 .desc io_init, near
202 .proc io_init
203 io_init:
33:../src/main.c ****
34:../src/main.c **** static void io_init( void)
35:../src/main.c **** {
205 .LMM10:
36:../src/main.c **** /* P0.0-7 011 AF OUT (Data/ LSB Address) */
37:../src/main.c **** spp( P0C_PG) ;
207 ; #APP
208 0014 C70A spp #2
209 ; #NO_APP
210 .LMM11:
38:../src/main.c **** P0C0R = 0xFF ;
212 0016 0CFF ld r0,#255
213 0018 09F0 ld @P0C0R,r0
214 .LMM12:
39:../src/main.c **** P0C1R = 0xFF ;
216 001a 09F1 ld @P0C1R,r0
217 .LMM13:
40:../src/main.c **** P0C2R = 0x00 ;
219 001c 90D1 clr r1
220 001e 19F2 ld @P0C2R,r1
221 .LMM14:
41:../src/main.c ****
42:../src/main.c **** /* P1.0-6 011 AF OUT (MSB Address)
43:../src/main.c **** P1.7 110 OUT OD (Row1)
44:../src/main.c **** */
45:../src/main.c **** spp( P1C_PG) ; /* same as P0C_PG */
223 ; #APP
224 0020 C70A spp #2
225 ; #NO_APP
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 5
226 .LMM15:
46:../src/main.c **** P1DR = 0xFF ;
228 0022 09E1 ld @P1DR,r0
229 .LMM16:
47:../src/main.c **** P1C0R = 0x7F ;
231 0024 F5F47F ld @P1C0R,#127
232 .LMM17:
48:../src/main.c **** P1C1R = 0xFF ;
234 0027 09F5 ld @P1C1R,r0
235 .LMM18:
49:../src/main.c **** P1C2R = 0x80 ;
237 0029 2C80 ld r2,#128
238 002b 29F6 ld @P1C2R,r2
239 .LMM19:
50:../src/main.c ****
51:../src/main.c **** /* P3.0 000 BID WP Schmitt Trigger (Col0)
52:../src/main.c **** P3.1 000 BID WP Schmitt Trigger (Col1)
53:../src/main.c **** P3.2 000 BID WP Schmitt Trigger (Col2)
54:../src/main.c **** P3.3 000 BID WP Schmitt Trigger (Col3)
55:../src/main.c **** P3.4 000 BID WP Schmitt Trigger (MS Data)
56:../src/main.c **** P3.5 000 BID WP Schmitt Trigger (MS CLK)
57:../src/main.c **** P3.6 011 AF OUT (ALE)
58:../src/main.c **** P3.7 110 OUT OD (Row0)
59:../src/main.c **** */
60:../src/main.c **** spp( P3C_PG) ;
241 ; #APP
242 002d C70A spp #2
243 ; #NO_APP
244 .LMM20:
61:../src/main.c **** P3DR = 0xFF ;
246 002f 09E3 ld @P3DR,r0
247 .LMM21:
62:../src/main.c **** P3C0R = 0x40 ;
249 0031 F5FC40 ld @P3C0R,#64
250 .LMM22:
63:../src/main.c **** P3C1R = 0xC0 ;
252 0034 3CC0 ld r3,#192
253 0036 39FD ld @P3C1R,r3
254 .LMM23:
64:../src/main.c **** P3C2R = 0x80 ;
256 0038 29FE ld @P3C2R,r2
257 .LMM24:
65:../src/main.c ****
66:../src/main.c **** /* P4.0 000 BID WP Schmitt Trigger (Col4)
67:../src/main.c **** P4.1 000 BID WP Schmitt Trigger (Col5)
68:../src/main.c **** P4.2 000 BID WP Schmitt Trigger (Col6)
69:../src/main.c **** P4.3 000 BID WP Schmitt Trigger (Col7)
70:../src/main.c **** */
71:../src/main.c **** spp( P4C_PG) ;
259 ; #APP
260 003a C70E spp #3
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