/****************************************************************/
/*                                                              */
/*           ST9+ Software Toolchain V6 Tutorial                */
/*                                                              */
/****************************************************************/

MEMORY
{
  ROM		  :	ORIGIN = 0x000000,	LENGTH = 20K,	MMU = IDPR0 IDPR1
  EXTRAM	  : ORIGIN = 0x03C000,	LENGTH = 16K,	MMU = IDPR2
  RAM	      : ORIGIN = 0x20F800,	LENGTH = 2K,	MMU = IDPR3
/*  RAM	  : ORIGIN = 0x03C000,	LENGTH = 32K,	MMU = IDPR3 IDPR2 */
/*  REGFILE (t) : ORIGIN = 0x0,		LENGTH = 208	*/ /* Groups 0 to 0x0C */
  REGFILE (t) : ORIGIN = 0x78,		LENGTH = 88		/* Groups 0 to 0x0C */
}

SECTIONS {

   _stack_size = DEFINED(_stack_size) ? _stack_size : 0x100;

  .init   :
  {
    *(.init) }						> ROM

  .fini   :
  {
    *(.fini) }						> ROM

  .text   :
  {
    *(.text) }						> ROM

  .rodata   :
  {
    *(.rodata) }					> ROM

  .secinfo   :
  {
    CREATE_SECINFO_TABLE }				> ROM

  .data   : AT (LOADADDR(.secinfo) + SIZEOF (.secinfo))
  {
    *(.data) }						> RAM

  .bss   :
  {
    *(.bss) *(COMMON) }					> RAM

  .stack   :
  {
    _stack_start = DEFINED( _stack_start) ? _stack_start : . ;
    . = . + _stack_size ;
    _stack_end = _stack_start + _stack_size ; }		> RAM

  .reg16_data :	AT (LOADADDR(.data) + SIZEOF (.data))
  {
 	*(.reg16_data)}					> REGFILE

  .reg16_bss :
  {
    *(.reg16_bss)}					> REGFILE

   .reg8_data :	AT (LOADADDR(.reg16_data) + SIZEOF (.reg16_data))
  {
    *(.reg8_data) }					> REGFILE

  .reg8_bss :
  {
    *(.reg8_bss)}					> REGFILE
}