?? lpc24xx.h
字號:
#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
#define CAN_CENTRAL_BASE_ADDR 0xE0040000
#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
#define CAN1_BASE_ADDR 0xE0044000
#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
#define CAN2_BASE_ADDR 0xE0048000
#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
/* MultiMedia Card Interface(MCI) Controller */
#define MCI_BASE_ADDR 0xE008C000
#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
/* I2S Interface Controller (I2S) */
#define I2S_BASE_ADDR 0xE0088000
#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
/* General-purpose DMA Controller */
#define DMA_BASE_ADDR 0xFFE04000
#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
/* DMA channel 0 registers */
#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
/* DMA channel 1 registers */
#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
/* USB Controller */
#define USB_INT_BASE_ADDR 0xE01FC1C0
#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
/* USB Device Interrupt Registers */
#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
/* USB Device Endpoint Interrupt Registers */
#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
/* USB Device Endpoint Realization Registers */
#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
/* USB Device Command Reagisters */
#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
/* USB Device Data Transfer Registers */
#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
/* USB Device DMA Registers */
#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
/* USB Host Controller */
#define USBHC_BASE_ADDR 0xFFE0C000
#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
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