library ieee;
　　use ieee.std_logic_1164.all;
　　use ieee.std_logic_arith.all;
　　use ieee.std_logic_unsigned.all;
　　entity aa is
　　port
　　( a1: in std_logic;
　　  b1: in std_logic;
　　  cin: in std_logic;
　　  bcdout: out std_logic;
　　  cout: out std_logic  );
　　end aa;
　　architecture arch of aa is
　　   signal y,c:std_logic;
　　begin 
　　      y<=a1 xor b1 xor cin;
　　      c<=(cin and a1) or (cin and b1) or (a1 and b1);
　　      bcdout<=y;
　　      cout<=c;
　　end arch;