//`define ETH_BIST                    // Bist for usage with Virtual Silicon RAMS


// Ethernet implemented in Xilinx Chips
// `define ETH_FIFO_XILINX             // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4            // Selection of the used memory for Buffer descriptors
                                      // Core is going to be implemented in Virtex FPGA and contains Virtex 
                                      // specific elements. 

// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM     // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)

`define ETH_MODER_ADR         8'h0    // 0x0 
`define ETH_INT_SOURCE_ADR    8'h1    // 0x4 
`define ETH_INT_MASK_ADR      8'h2    // 0x8 
`define ETH_IPGT_ADR          8'h3    // 0xC 
`define ETH_IPGR1_ADR         8'h4    // 0x10
`define ETH_IPGR2_ADR         8'h5    // 0x14
`define ETH_PACKETLEN_ADR     8'h6    // 0x18
`define ETH_COLLCONF_ADR      8'h7    // 0x1C
`define ETH_TX_BD_NUM_ADR     8'h8    // 0x20
`define ETH_CTRLMODER_ADR     8'h9    // 0x24
`define ETH_MIIMODER_ADR      8'hA    // 0x28
`define ETH_MIICOMMAND_ADR    8'hB    // 0x2C
`define ETH_MIIADDRESS_ADR    8'hC    // 0x30
`define ETH_MIITX_DATA_ADR    8'hD    // 0x34
`define ETH_MIIRX_DATA_ADR    8'hE    // 0x38
`define ETH_MIISTATUS_ADR     8'hF    // 0x3C
`define ETH_MAC_ADDR0_ADR     8'h10   // 0x40
`define ETH_MAC_ADDR1_ADR     8'h11   // 0x44
`define ETH_HASH0_ADR         8'h12   // 0x48
`define ETH_HASH1_ADR         8'h13   // 0x4C
`define ETH_TX_CTRL_ADR       8'h14   // 0x50
`define ETH_RX_CTRL_ADR       8'h15   // 0x54


`define ETH_MODER_DEF         17'h0A000
`define ETH_INT_MASK_DEF      7'h0
`define ETH_IPGT_DEF          7'h12
`define ETH_IPGR1_DEF         7'h0C
`define ETH_IPGR2_DEF         7'h12
`define ETH_PACKETLEN_DEF     32'h00400600
`define ETH_COLLCONF0_DEF     6'h3f
`define ETH_COLLCONF1_DEF     4'hF
`define ETH_TX_BD_NUM_DEF     8'h40
`define ETH_CTRLMODER_DEF     3'h0
`define ETH_MIIMODER_DEF      10'h064
`define ETH_MIIADDRESS0_DEF   5'h00
`define ETH_MIIADDRESS1_DEF   5'h00
`define ETH_MIITX_DATA_DEF    16'h0000
`define ETH_MIIRX_DATA_DEF    16'h0000
`define ETH_MIISTATUS_DEF     32'h00000000
`define ETH_MAC_ADDR0_DEF     32'h00000000
`define ETH_MAC_ADDR1_DEF     16'h0000
`define ETH_HASH0_DEF         32'h00000000
`define ETH_HASH1_DEF         32'h00000000
`define ETH_RX_CTRL_DEF       16'h0


`define ETH_MODER_WIDTH       17
`define ETH_INT_SOURCE_WIDTH  7
`define ETH_INT_MASK_WIDTH    7
`define ETH_IPGT_WIDTH        7
`define ETH_IPGR1_WIDTH       7
`define ETH_IPGR2_WIDTH       7
`define ETH_PACKETLEN_WIDTH   32
`define ETH_TX_BD_NUM_WIDTH   8
`define ETH_CTRLMODER_WIDTH   3
`define ETH_MIIMODER_WIDTH    9
`define ETH_MIITX_DATA_WIDTH  16
`define ETH_MIIRX_DATA_WIDTH  16
`define ETH_MIISTATUS_WIDTH   3
`define ETH_MAC_ADDR0_WIDTH   32
`define ETH_MAC_ADDR1_WIDTH   16
`define ETH_HASH0_WIDTH       32
`define ETH_HASH1_WIDTH       32
`define ETH_TX_CTRL_WIDTH     17
`define ETH_RX_CTRL_WIDTH     16


// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS

// Settings for TX FIFO
`define ETH_TX_FIFO_CNT_WIDTH  5
`define ETH_TX_FIFO_DEPTH      16
`define ETH_TX_FIFO_DATA_WIDTH 32

// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH  5
`define ETH_RX_FIFO_DEPTH      16
`define ETH_RX_FIFO_DATA_WIDTH 32

// Burst length
`define ETH_BURST_LENGTH       4    // Change also ETH_BURST_CNT_WIDTH
`define ETH_BURST_CNT_WIDTH    3    // The counter must be width enough to count to ETH_BURST_LENGTH

// WISHBONE interface is Revision B3 compliant (uncomment when needed)
//`define ETH_WISHBONE_B3