/* Name: usbdrvasm16.S * Project: AVR USB driver * Author: Christian Starkjohann * Creation Date: 2007-06-15 * Tabsize: 4 * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt) * Revision: $Id$ *//* Do not link this file! Link usbdrvasm.S instead, which includes the * appropriate implementation! *//*General Description:This file is the 16 MHz version of the asssembler part of the USB driver. Itrequires a 16 MHz crystal (not a ceramic resonator and not a calibrated RCoscillator).See usbdrv.h for a description of the entire driver.Since almost all of this code is timing critical, don't change unless youreally know what you are doing! Many parts require not only a maximum numberof CPU cycles, but even an exact number of cycles!*/;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte; Numbers in brackets are clocks counted from center of last sync bit; when instruction startsSIG_INTERRUPT0:;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt    push    YL                  ;[-25] push only what is necessary to sync with edge ASAP    in      YL, SREG            ;[-23]    push    YL                  ;[-22]    push    YH                  ;[-20];----------------------------------------------------------------------------; Synchronize with sync pattern:;----------------------------------------------------------------------------;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K];sync up with J to K edge during sync pattern -- use fastest possible loops;first part has no timeout because it waits for IDLE or SE1 (== disconnected)waitForJ:    sbis    USBIN, USBMINUS     ;[-18] wait for D- == 1    rjmp    waitForJwaitForK:;The following code results in a sampling window of < 1/4 bit which meets the spec.    sbis    USBIN, USBMINUS     ;[-15]    rjmp    foundK              ;[-14]    sbis    USBIN, USBMINUS    rjmp    foundK    sbis    USBIN, USBMINUS    rjmp    foundK    sbis    USBIN, USBMINUS    rjmp    foundK    sbis    USBIN, USBMINUS    rjmp    foundK    sbis    USBIN, USBMINUS    rjmp    foundK    rjmp    sofErrorfoundK:                         ;[-12];{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling];we have 1 bit time for setup purposes, then sample again. Numbers in brackets;are cycles from center of first sync (double K) bit after the instruction    push    bitcnt              ;[-12];   [---]                       ;[-11]    lds     YL, usbInputBufOffset;[-10];   [---]                       ;[-9]    clr     YH                  ;[-8]    subi    YL, lo8(-(usbRxBuf));[-7] [rx loop init]    sbci    YH, hi8(-(usbRxBuf));[-6] [rx loop init]    push    shift               ;[-5];   [---]                       ;[-4]    ldi     bitcnt, 0x55        ;[-3] [rx loop init]    sbis    USBIN, USBMINUS     ;[-2] we want two bits K (sample 2 cycles too early)    rjmp    haveTwoBitsK        ;[-1]    pop     shift               ;[0] undo the push from before    pop     bitcnt              ;[2] undo the push from before    rjmp    waitForK            ;[4] this was not the end of sync, retry; The entire loop from waitForK until rjmp waitForK above must not exceed two; bit times (= 21 cycles).;----------------------------------------------------------------------------; push more registers and initialize values while we sample the first bits:;----------------------------------------------------------------------------haveTwoBitsK:    push    x1              ;[1]    push    x2              ;[3]    push    x3              ;[5]    ldi     shift, 0        ;[7]    ldi     x3, 1<<4        ;[8] [rx loop init] first sample is inverse bit, compensate that    push    x4              ;[9] == leap    in      x1, USBIN       ;[11] <-- sample bit 0    andi    x1, USBMASK     ;[12]    bst     x1, USBMINUS    ;[13]    bld     shift, 7        ;[14]    push    cnt             ;[15]    ldi     leap, 0         ;[17] [rx loop init]    ldi     cnt, USB_BUFSIZE;[18] [rx loop init]    rjmp    rxbit1          ;[19] arrives at [21];----------------------------------------------------------------------------; Receiver loop (numbers in brackets are cycles within byte after instr);----------------------------------------------------------------------------unstuff6:    andi    x2, USBMASK ;[03]    ori     x3, 1<<6    ;[04] will not be shifted any more    andi    shift, ~0x80;[05]    mov     x1, x2      ;[06] sampled bit 7 is actually re-sampled bit 6    subi    leap, 3     ;[07] since this is a short (10 cycle) bit, enforce leap bit    rjmp    didUnstuff6 ;[08]unstuff7:    ori     x3, 1<<7    ;[09] will not be shifted any more    in      x2, USBIN   ;[00] [10]  re-sample bit 7    andi    x2, USBMASK ;[01]    andi    shift, ~0x80;[02]    subi    leap, 3     ;[03] since this is a short (10 cycle) bit, enforce leap bit    rjmp    didUnstuff7 ;[04]unstuffEven:    ori     x3, 1<<6    ;[09] will be shifted right 6 times for bit 0    in      x1, USBIN   ;[00] [10]    andi    shift, ~0x80;[01]    andi    x1, USBMASK ;[02]    breq    se0         ;[03]    subi    leap, 3     ;[04] since this is a short (10 cycle) bit, enforce leap bit    nop                 ;[05]    rjmp    didUnstuffE ;[06]unstuffOdd:    ori     x3, 1<<5    ;[09] will be shifted right 4 times for bit 1    in      x2, USBIN   ;[00] [10]    andi    shift, ~0x80;[01]    andi    x2, USBMASK ;[02]    breq    se0         ;[03]    subi    leap, 3     ;[04] since this is a short (10 cycle) bit, enforce leap bit    nop                 ;[05]    rjmp    didUnstuffO ;[06]rxByteLoop:    andi    x1, USBMASK ;[03]    eor     x2, x1      ;[04]    subi    leap, 1     ;[05]    brpl    skipLeap    ;[06]    subi    leap, -3    ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte    nop                 ;1skipLeap:    subi    x2, 1       ;[08]    ror     shift       ;[09]didUnstuff6:    cpi     shift, 0xfc ;[10]    in      x2, USBIN   ;[00] [11] <-- sample bit 7    brcc    unstuff6    ;[01]    andi    x2, USBMASK ;[02]    eor     x1, x2      ;[03]    subi    x1, 1       ;[04]    ror     shift       ;[05]didUnstuff7:    cpi     shift, 0xfc ;[06]    brcc    unstuff7    ;[07]    eor     x3, shift   ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others    st      y+, x3      ;[09] store datarxBitLoop:    in      x1, USBIN   ;[00] [11] <-- sample bit 0/2/4    andi    x1, USBMASK ;[01]    eor     x2, x1      ;[02]    andi    x3, 0x3f    ;[03] topmost two bits reserved for 6 and 7    subi    x2, 1       ;[04]    ror     shift       ;[05]    cpi     shift, 0xfc ;[06]    brcc    unstuffEven ;[07]didUnstuffE:    lsr     x3          ;[08]    lsr     x3          ;[09]rxbit1:    in      x2, USBIN   ;[00] [10] <-- sample bit 1/3/5    andi    x2, USBMASK ;[01]    breq    se0         ;[02]    eor     x1, x2      ;[03]    subi    x1, 1       ;[04]    ror     shift       ;[05]    cpi     shift, 0xfc ;[06]    brcc    unstuffOdd  ;[07]didUnstuffO:    subi    bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3    brcs    rxBitLoop   ;[09]    subi    cnt, 1      ;[10]    in      x1, USBIN   ;[00] [11] <-- sample bit 6    brcc    rxByteLoop  ;[01]    rjmp    ignorePacket; overflow;----------------------------------------------------------------------------; Processing of received packet (numbers in brackets are cycles after center of SE0);----------------------------------------------------------------------------;This is the only non-error exit point for the software receiver loop;we don't check any CRCs here because there is no time left.#define token   x1se0:    subi    cnt, USB_BUFSIZE    ;[5]    neg     cnt                 ;[6]    cpi     cnt, 3              ;[7]    ldi     x2, 1<<USB_INTR_PENDING_BIT ;[8]    out     USB_INTR_PENDING, x2;[9] clear pending intr and check flag later. SE0 should be over.    brlo    doReturn            ;[10] this is probably an ACK, NAK or similar packet    sub     YL, cnt             ;[11]    sbci    YH, 0               ;[12]    ld      token, y            ;[13]    cpi     token, USBPID_DATA0 ;[15]    breq    handleData          ;[16]    cpi     token, USBPID_DATA1 ;[17]    breq    handleData          ;[18]    ldd     x2, y+1             ;[19] ADDR and 1 bit endpoint number    mov     x3, x2              ;[21] store for endpoint number    andi    x2, 0x7f            ;[22] x2 is now ADDR    lds     shift, usbDeviceAddr;[23]    cp      x2, shift           ;[25]overflow:                       ; This is a hack: brcs overflow will never have Z flag set    brne    ignorePacket        ;[26] packet for different address    cpi     token, USBPID_IN    ;[27]    breq    handleIn            ;[28]    cpi     token, USBPID_SETUP ;[29]    breq    handleSetupOrOut    ;[30]    cpi     token, USBPID_OUT   ;[31]    breq    handleSetupOrOut    ;[32];   rjmp    ignorePacket        ;fallthrough, should not happen anyway.ignorePacket:    clr     shift    sts     usbCurrentTok, shift