/*   Do *not* directly modify this file.  It was    *//*   generated by the Configuration Tool; any  *//*   changes risk being overwritten.                *//* INPUT emiface0.cdb *//*  Include Header File  */#include "emiface0cfg.h"#ifdef __cplusplus#pragma CODE_SECTION(".text:CSL_cfgInit")#else#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")#endif#ifdef __cplusplus#pragma FUNC_EXT_CALLED()#else#pragma FUNC_EXT_CALLED(CSL_cfgInit)#endif/*  Config Structures */EDMA_Config EMIFA_EDMA = {    0x00000000,        /*  Option  */    0x00200000,        /*  Source Address - Numeric   */    0x00000000,        /*  Transfer Counter - Numeric  */    0x00000000,        /*  Destination Address - Numeric   */    0x00000000,        /*  Index register - Numeric  */    0x00000000         /*  Element Count Reload and Link Address  */};EMIFA_Config emifaCfg0 = {    0x000120D4,        /*  Global Control Reg. (GBLCTL)   */    0xFFFFFFD3,        /*  CE0 Space Control Reg. (CECTL0)   */    0xFFFFFF03,        /*  CE1 Space Control Reg. (CECTL1)   */    0xFFFFFF23,        /*  CE2 Space Control Reg. (CECTL2)   */    0xFFFFFF23,        /*  CE3 Space Control Reg. (CECTL3)   */    0x4748F000,        /*  SDRAM Control Reg.(SDCTL)   */    0x005DC5DC,        /*  SDRAM Timing Reg.(SDTIM)   */    0x00175F3F,        /*  SDRAM Extended Reg.(SDEXT)   */    0x00000043,        /*  CE0 Space Secondary Control Reg. (CESEC0)  */    0x00000042,        /*  CE1 Space Secondary Control Reg. (CESEC1)  */    0x00000002,        /*  CE2 Space Secondary Control Reg. (CESEC2)  */    0x00000002         /*  CE3 Space Secondary Control Reg. (CESEC3)  */};EMIFB_Config emifbCfg0 = {    0x000320B4,        /*  Global Control Reg. (GBLCTL)   */    0x3FF1FF00,        /*  CE0 Space Control Reg. (CECTL0)   */    0xFFFFFF03,        /*  CE1 Space Control Reg. (CECTL1)   */    0xFFFFFF03,        /*  CE2 Space Control Reg. (CECTL2)   */    0xFFFFFF03,        /*  CE3 Space Control Reg. (CECTL3)   */    0x0348F000,        /*  SDRAM Control Reg.(SDCTL)   */    0x005DC5DC,        /*  SDRAM Timing Reg.(SDTIM)   */    0x00175F3F,        /*  SDRAM Extended Reg.(SDEXT)   */    0x00000002,        /*  CE0 Space Secondary Control Reg. (CESEC0)  */    0x00000002,        /*  CE1 Space Secondary Control Reg. (CESEC1)  */    0x00000002,        /*  CE2 Space Secondary Control Reg. (CESEC2)  */    0x00000002         /*  CE3 Space Secondary Control Reg. (CESEC3)  */};MCBSP_Config mcbspCfg0 = {    0x00000000,        /*  Serial Port Control Reg. (SPCR)   */    0x00000000,        /*  Receiver Control Reg. (RCR)   */    0x00000000,        /*  Transmitter Control Reg. (XCR)   */    0x20000001,        /*  Sample-Rate Generator Reg. (SRGR)   */    0x00000000,        /*  Multichannel Control Reg. (MCR)   */    0x00000000,        /*  Enhanced Receiver Channel Enable(RCERE0)   */    0x00000000,        /*  Enhanced Receiver Channel Enable(RCERE1)   */    0x00000000,        /*  Enhanced Receiver Channel Enable(RCERE2)   */    0x00000000,        /*  Enhanced Receiver Channel Enable(RCERE3)   */    0x00000000,        /*  Enhanced Transmitter Channel Enable(XCERE0)   */    0x00000000,        /*  Enhanced Transmitter Channel Enable(XCERE1)   */    0x00000000,        /*  Enhanced Transmitter Channel Enable(XCERE2)   */    0x00000000,        /*  Enhanced Transmitter Channel Enable(XCERE3)   */    0x00002000         /*  Pin Control Reg. (PCR)   */};/*  Handles  *//* *  ======== CSL_cfgInit() ========   */void CSL_cfgInit(){}