?? multi_baudrate_generator.vhd
字號(hào):
-- 庫(kù)聲明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;
-- 實(shí)體聲明
entity multi_baudrate_generator is
-- 類屬參數(shù)聲明
-- generic (
-- FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;
-- RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC );
-- 端口聲明
port (
clk : in std_logic;
reset_n : in std_logic;
ce : in std_logic;
bcr: in std_logic_vector(3 downto 0);
bcrs_n: in std_logic;
bg_out : out std_logic);
--- indicator : out std_logic );
end multi_baudrate_generator;
--}} End of automatically maintained section
-- 結(jié)構(gòu)體
architecture multi_baudrate_generator of multi_baudrate_generator is
signal bcr_s:std_logic_vector(3 downto 0);
signal FULL_PULSE_COUNT:BD_COUNT;
signal RISE_PULSE_COUNT:BD_COUNT;
begin
bcr_latch_proc:process(reset_n,bcrs_n,bcr_s)
begin
if(reset_n='0') then
bcr_s<="0101";
elsif(bcrs_n='0') then
bcr_s<=bcr;
end if;
end process bcr_latch_proc;
baudrate_set_proc:process(bcr_s) -----波特率設(shè)定
begin
case bcr_s is
when "0000" =>
FULL_PULSE_COUNT<=28409;
RISE_PULSE_COUNT<=14205;
when "0001" =>
FULL_PULSE_COUNT<=10417;
RISE_PULSE_COUNT<=5208;
when "0010" =>
FULL_PULSE_COUNT<=2604;
RISE_PULSE_COUNT<=1302;
when "0011" =>
FULL_PULSE_COUNT<=1302;
RISE_PULSE_COUNT<=651;
when "0100" =>
FULL_PULSE_COUNT<=651;
RISE_PULSE_COUNT<=326;
when "0101" =>
FULL_PULSE_COUNT<=326;
RISE_PULSE_COUNT<=163;
when "0110" =>
FULL_PULSE_COUNT<=163;
RISE_PULSE_COUNT<=81;
when "0111" =>
FULL_PULSE_COUNT<=81;
RISE_PULSE_COUNT<=41;
when "1000" =>
FULL_PULSE_COUNT<=54;
RISE_PULSE_COUNT<=27;
when "1001" =>
FULL_PULSE_COUNT<=27;
RISE_PULSE_COUNT<=14;
when "1010" =>
FULL_PULSE_COUNT<=14;
RISE_PULSE_COUNT<=7;
when "1011" =>
FULL_PULSE_COUNT<=7;
RISE_PULSE_COUNT<=3;
when "1100" =>
FULL_PULSE_COUNT<=3;
RISE_PULSE_COUNT<=2;
when others =>
end case;
end process baudrate_set_proc;
-- enter your statements here --
-- 主過(guò)程
-- main process
main : process( clk, reset_n )
variable clk_count : BD_COUNT;
begin
-- 判斷復(fù)位信號(hào)
if reset_n = '0' then
bg_out <= '0';
--- indicator <= '0';
clk_count := 0;
-- 在時(shí)鐘信號(hào)的上升沿動(dòng)作
elsif rising_edge(clk) then
-- 判斷使能信號(hào)
if ce = '1' then
-- 經(jīng)過(guò)了RISE_PULSE_COUNT個(gè)計(jì)數(shù),數(shù)脈沖上升
if clk_count = RISE_PULSE_COUNT-1 then -- pulse rise
bg_out <= '1';
clk_count := clk_count+1;
-- 經(jīng)過(guò)了FULL_PULSE_COUNT個(gè)計(jì)數(shù),數(shù)脈沖下降
elsif clk_count = FULL_PULSE_COUNT-1 then -- indicator output and pulse fall
-- 輸出提示信號(hào),使其為高
---- indicator <= '1';
bg_out <= '0';
-- 重置計(jì)數(shù)器計(jì)數(shù)為0
clk_count := 0;
-- 恢復(fù)提示信號(hào)為低
elsif clk_count = 0 then
------ indicator <= '0';
clk_count := clk_count+1;
else
clk_count := clk_count+1;
end if;
end if;
end if;
end process;
end multi_baudrate_generator;
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