module uartr(clk,rst,rxd,out,ri,cri);

input clk,rst;
input rxd;
output[7:0] out;
output ri;
input cri;

reg ri;
reg[7:0] out;

reg[11:0] cnt;
reg[3:0] m;
reg rip;
reg[7:0] sft;

always@(posedge(clk))
begin
  if(rst==1)begin
    m=0;
    rip=0;
  end else begin
    case(m)
      0:begin
        if(rxd==0)begin
          cnt=0;
          m=1;
        end
      end
      1:begin
        cnt=cnt+1;
        if(cnt>=1719)begin
          cnt=0;
          m=2;
        end
      end
      2,3,4,5,6,7,8,9:begin
        cnt=cnt+1;
        if(cnt>=3437)begin
          cnt=0;
          sft=sft>>1;
          sft[7]=rxd;
          m=m+1;
        end
      end
      10:begin
        cnt=cnt+1;
        if(cnt>=3437)begin
          m=m+1;
        end
      end
      11:begin
        if(rxd==1)begin
          rip=1;
          out=sft;
          m=0;
        end
      end
    endcase
  end
end

always@(posedge(clk))
begin
  if(cri==1)begin
    ri=0;
  end else if(rip==1)begin
    ri=1;
  end
end

endmodule