--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="MAX II" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=4 aleb clock dataa datab CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 15 
SUBDESIGN cmpr_65i
( 
	aleb	:	output;
	clock	:	input;
	dataa[3..0]	:	input;
	datab[3..0]	:	input;
) 
VARIABLE
	aeb_int	:	WIRE;
	alb_int	:	WIRE;
	aleb_dffe[0..0]	:	DFFE;
BEGIN 
	IF (dataa[] == datab[]) THEN
		aeb_int = VCC;
	ELSE
		aeb_int = GND;
	END IF;
	IF (dataa[] < datab[]) THEN
		alb_int = VCC;
	ELSE
		alb_int = GND;
	END IF;
	aleb_dffe[0].d = alb_int # aeb_int;
	aleb = aleb_dffe[0].q;
	aleb_dffe[].clk = clock;
END;
--VALID FILE