module receive_control         (sample_clk,                                reset,                                syn_global_reset,                                begin_decode,                                code,                                assert_8,                                assert_16,                                assert_64,                                crc_right,                                read_in,                                shift_code_receive,                                shift_addr_receive,                                shift_mask_receive,                                shift_data_receive,                                shift_crc_receive,                                receive_crc_check,                                ena_crc,                                set_count_receive,                                stop_receive,                                crc_riorwr);//recent modification:5/10 //output ports modified to internal ports:state,nextstate       input sample_clk;input reset;input syn_global_reset;input begin_decode;input [8:1] code;//only need to know the low 4 bits of the command codeinput assert_8;input assert_16;input assert_64;input crc_right;input read_in;output shift_code_receive;output shift_addr_receive;output shift_mask_receive;output shift_data_receive;output shift_crc_receive;output receive_crc_check;output set_count_receive;reg set_count_receive;output stop_receive;reg stop_receive;output [2:1] crc_riorwr;reg [2:1] crc_riorwr;reg [4:1] state;reg [4:1] nextstate;parameter GROUP_SELECT_NE=8'b0000_0001,          READ=8'b0000_1100,          WRITE=8'b0000_1101;parameter S10=4'b0000,          S1=4'b0001,          S2=4'b0011,          S3=4'b0010,          S4=4'b0110,          S5=4'b0111,          S6=4'b0101,          S7=4'b1011,          S8=4'b1001,          S9=4'b1101,          S0=4'b1100;        always@(posedge sample_clk or negedge reset)begin    if(!reset)      begin          state<=S10;      end   else if(syn_global_reset)      begin          state<=S10;      end   else if(begin_decode)     begin        state<=S0;     end   else       begin        state<=nextstate;      endendalways@(state or assert_8 or assert_64 or assert_16 or code or crc_right)begin    case(state)        S0:           begin               nextstate<=S1;           end        S1:           begin               if(assert_8)                 begin                     nextstate<=S2;                 end               else                 begin                     nextstate<=S1;                 end           end        S2:           begin                case(code)                    GROUP_SELECT_NE:                                    begin                                        nextstate<=S3;                                    end                    READ:                         begin                             nextstate<=S5;                         end                    WRITE:                          begin                              nextstate<=S5;                          end                    default:                            begin                                 nextstate<=S2;                            end                endcase           end        S3:           begin               if(assert_8)                 begin                     case(code)                         GROUP_SELECT_NE:                                         begin                                             nextstate<=S4;                                         end                         READ:                              begin                                  nextstate<=S6;                              end                         WRITE:                               begin                                   nextstate<=S4;                               end                         default:                                 begin                                     nextstate<=S3;                                 end                     endcase                 end               else                   begin                       nextstate<=S3;                   end           end        S4:           begin               if(assert_8)                  begin                      case(code)                          GROUP_SELECT_NE:                                          begin                                              nextstate<=S5;                                          end                          WRITE:                                begin                                   nextstate<=S6;                                 end                          default:                                  begin                                      nextstate<=S4;                                  end                      endcase                  end               else                   begin                       nextstate<=S4;                   end           end        S5:           begin               if(assert_64)                  begin                      case(code)                          GROUP_SELECT_NE:                                          begin                                              nextstate<=S6;                                          end                          READ:                               begin                                   nextstate<=S3;                               end                          WRITE:                                begin                                    nextstate<=S3;                                end                          default:                                  begin                                      nextstate<=S5;                                  end                      endcase                  end               else                   begin                       nextstate<=S5;                   end           end        S6:           begin               if(assert_16)                  begin                      nextstate<=S7;                  end               else                  begin                      nextstate<=S6;                  end           end        S7:           begin               if(crc_right)                  begin                      nextstate<=S8;                  end               else                  begin                      nextstate<=S9;                  end           end        S8:           begin               nextstate<=S8;           end        S9:           begin               nextstate<=S9;           end        S10:            begin                nextstate<=S10;            end        default:                begin                    nextstate<=S10;                end    endcaseendwire ena_code;wire ena_addr;wire ena_mask;wire ena_data;output ena_crc;assign ena_code=(state==S1);assign ena_addr=(state==S3);assign ena_mask=(state==S4);assign ena_data=(state==S5);assign ena_crc=(state==S6)||(state==S7);assign receive_crc_check=ena_code||ena_addr||ena_mask||ena_data||ena_crc;assign shift_code_receive=ena_code&&read_in;assign shift_addr_receive=ena_addr&&read_in;assign shift_mask_receive=ena_mask&&read_in;assign shift_data_receive=ena_data&&read_in;assign shift_crc_receive=receive_crc_check&&read_in;always@(state)begin    case(state)        S8:           begin               crc_riorwr=2'b01;           end        S9:           begin               crc_riorwr=2'b10;           end        default:                begin                    crc_riorwr=2'b00;                end    endcaseendalways@(state or assert_16)begin    case(state)        S6:           begin               if(assert_16)                  begin                      stop_receive=1'b1;                  end               else                   begin                       stop_receive=1'b0;                   end           end        S7:           begin               stop_receive=1'b1;           end        S8:           begin               stop_receive=1'b1;           end        S9:           begin               stop_receive=1'b1;           end        default:                begin                    stop_receive=1'b0;                end    endcaseendalways@(state or assert_8 or assert_64)begin    case(state)        S1:           begin               if(assert_8)                  begin                      set_count_receive=1'b1;                  end               else                  begin                      set_count_receive=1'b0;                  end           end        S3:           begin               if(assert_8)                  begin                      set_count_receive=1'b1;                  end               else                  begin                      set_count_receive=1'b0;                  end           end        S4:           begin               if(assert_8)                  begin                      set_count_receive=1'b1;                  end               else                  begin                      set_count_receive=1'b0;                  end           end        S5:           begin               if(assert_64)                  begin                      set_count_receive=1'b1;                  end               else                  begin                      set_count_receive=1'b0;                  end           end        S7:           begin              set_count_receive=1'b1;           end        default:               begin                   set_count_receive=1'b0;               end    endcaseendendmodule