?? memcfg.a
字號:
;************************************************
; Copyright (c) 2003. Samsung Electronics, co. ltd All rights reserved.
; NAME : MEMCFG.A
; DESC : Memory bank configuration file
;************************************************
;Memory Area(SMDK24A0)
;SROM | Bank 0 16bit AMD or Strata (0x0000_0000-0x03ff_ffff)
;SROM | Bank 1 16bit Ethernet (0x0400_0000-0x05ff_ffff)
; 8bit MODEM IF (0x0600_0000-0x07ff_ffff)
;SROM | Bank 2 16bit AMD or Strata (0x0800_0000-0x09ff_ffff)
;SDRAM| System Group;Xp 32bit(64MB) Normal (0x1000_0000-0x13ff_ffff)
;SDRAM| Image Subsystem;Xd 32bit(32MB) Mobile (0x2000_0000-0x2200_0000)
;After drawing schematic of proper memory configuration, We must re-set Port 0 bank0/1/2 and Port1/2 bank 0/1.
;BWSCON
DW8 EQU (0x0)
DW16 EQU (0x1)
WAIT EQU (0x1<<1)
UBLB EQU (0x1<<2)
B1_BWSCON EQU (DW16+WAIT+UBLB)
B2_BWSCON EQU (DW16)
B2_CS_SROM EQU (0x0)
B2_CS_NAND EQU (0x1)
;
; FCLK 50000000
;
;FCLK EQU 50000000
[ {FALSE}
;FCLK = 50000000
;Set HCLKdiv&PCLKdiv 1:1:1
HCLKdiv EQU 0x0
PCLKdiv EQU 0x0
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x3 ;10 clks=200ns@50Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x0 ;0 clk
B1_Tacc EQU 0x3 ;10 clks
B1_Tcoh EQU 0x0 ;0 clk
B1_Tcah EQU 0x0 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x3 ;10 clks
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Mobile SDRAM:K4S56163LC-RG/S75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x2 ;3 clks=60ns@50MHz;Min45ns
SDRAM_Trc EQU 0x3 ;4 clks=80ns@50MHz;Min65ns
SDRAM_Trcd EQU 0x1 ;2 clks=40ns@50MHz;Min20ns
SDRAM_Trp EQU 0x1 ;2 clks=40ns@50MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 390 ;period= 7.8us, HCLK=50Mhz, ( 7.8*50)
]
[ {FALSE}
;FCLK = 84000000
;Set HCLKdiv&PCLKdiv 1:1:2
HCLKdiv EQU 0x0
PCLKdiv EQU 0x1
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x5 ;14 clks=166.65ns@84Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x0 ;0 clk
B1_Tacc EQU 0x5 ;14 clks
B1_Tcoh EQU 0x0 ;0 clk
B1_Tcah EQU 0x0 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x5 ;14 clks
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Mobile SDRAM:K4S56163LC-RG/S75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x4 ;5 clks=59.52ns@84MHz;Min45ns
SDRAM_Trc EQU 0x6 ;7 clks=83.32ns@84MHz;Min65ns
SDRAM_Trcd EQU 0x2 ;3 clks=35.71ns@84MHz;Min20ns
SDRAM_Trp EQU 0x2 ;3 clks=35.71ns@84MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 655 ;period= 7.8us, HCLK=84Mhz, ( 7.8*84)
]
[ {FALSE}
;FCLK = 202000000
;Set HCLKdiv&PCLKdiv 1:2:4
HCLKdiv EQU 0x1
PCLKdiv EQU 0x1
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x6 ;16 clks=158.4ns@101Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x0 ;0 clk
B1_Tacc EQU 0x6 ;16 clks
B1_Tcoh EQU 0x0 ;0 clk
B1_Tcah EQU 0x0 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x6 ;16 clks
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Mobile SDRAM:K4S56163LC-RG/S75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x5 ;6 clks=59.4ns@101MHz;Min45ns
SDRAM_Trc EQU 0x7 ;8 clks=79.2ns@101MHz;Min65ns
SDRAM_Trcd EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_Trp EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 787 ;period= 7.8us, HCLK=101Mhz, ( 7.8*101)
]
[ {FALSE}
;FCLK = 203000000
;Set HCLKdiv&PCLKdiv 1:2:4
HCLKdiv EQU 0x1
PCLKdiv EQU 0x1
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x6 ;16 clks=158.4ns@101Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x2 ;0 clk
;B1_Tacc EQU 0x6 ;16 clks
B1_Tacc EQU 0x6 ;20 clks
B1_Tcoh EQU 0x2 ;0 clk
B1_Tcah EQU 0x2 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x6 ;16 clks
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Mobile SDRAM:K4S56163LC-RG/S75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x5 ;6 clks=59.4ns@101MHz;Min45ns
SDRAM_Trc EQU 0x7 ;8 clks=79.2ns@101MHz;Min65ns
SDRAM_Trcd EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_Trp EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 787 ;period= 7.8us, HCLK=101Mhz, ( 7.8*101)
]
[{TRUE}
;FCLK = 204000000
;Set HCLKdiv&PCLKdiv 1:2:4
HCLKdiv EQU 0x1
PCLKdiv EQU 0x1
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x6 ;16 clks=158.4ns@101Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x2 ;0 clk
;B1_Tacc EQU 0x6 ;16 clks
B1_Tacc EQU 0x6 ;20 clks
B1_Tcoh EQU 0x2 ;0 clk
B1_Tcah EQU 0x2 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x6 ;16 clks
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Mobile SDRAM:K4S56163LC-RG/S75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x5 ;6 clks=59.4ns@101MHz;Min45ns
SDRAM_Trc EQU 0x7 ;8 clks=79.2ns@101MHz;Min65ns
SDRAM_Trcd EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_Trp EQU 0x2 ;3 clks=29.7ns@101MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 796 ;period= 7.8us, HCLK=101Mhz, ( 7.8*101)
]
[ {FALSE}
; FCLK = 220000000
;Set HCLKdiv&PCLKdiv 1:2:4
HCLKdiv EQU 0x1
PCLKdiv EQU 0x1
;SROM | Bank 0 parameter
B0_Tacs EQU 0x0 ;0 clk
B0_Tcos EQU 0x0 ;0 clk
B0_Tacc EQU 0x7 ;20 clks=181.80ns@110Mhz;AMD=Min90ns/Strata=150ns
B0_Tcoh EQU 0x0 ;0 clk
B0_Tcah EQU 0x0 ;0 clk
B0_Tacp EQU 0x0
B0_PMC EQU 0x0 ;normal
;SROM | Bank 1 parameter
B1_Tacs EQU 0x0 ;0 clk
B1_Tcos EQU 0x0 ;0 clk
B1_Tacc EQU 0x7 ;20 clks
B1_Tcoh EQU 0x0 ;0 clk
B1_Tcah EQU 0x0 ;0 clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;SROM | Bank 2 parameter
B2_Tacs EQU 0x0 ;0 clk
B2_Tcos EQU 0x0 ;0 clk
B2_Tacc EQU 0x7 ;20 clk
B2_Tcoh EQU 0x0 ;0 clk
B2_Tcah EQU 0x0 ;0 clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;SDRAM| System Group;Xp parameter(Normal SDRAM:K4S561632C-TCL75:133Mhz,CL=3)
SDRAM_PWRDN EQU 0x1 ;support sdram power down control
SDRAM_Tras EQU 0x4 ;5 clks=54.54ns@110MHz;Min45ns
SDRAM_Trc EQU 0x7 ;8 clks=72.72ns@110MHz;Min65ns
SDRAM_Trcd EQU 0x2 ;3 clks=27.27ns@110MHz;Min20ns
SDRAM_Trp EQU 0x2 ;3 clks=27.27ns@110MHz;Min20ns
SDRAM_B1DEN EQU 0x0 ;Initial Value
SDRAM_B0DEN EQU 0x3 ;256Mb((4M*16bit*4bank)*2)
SDRAM_CL EQU 0x3 ;3clk
SDRAM_AP EQU 0x0 ;enable auto pre-charge
SDRAM_DW EQU 0x0 ;32bit
SDRAM_CFG EQU (SDRAM_PWRDN<<20)+(SDRAM_Tras<<16)+(SDRAM_Trc<<12)+(SDRAM_Trcd<<10)+(SDRAM_Trp<<8)+(SDRAM_B1DEN<<6)+(SDRAM_B0DEN<<4)+(SDRAM_CL<<2)+(SDRAM_AP<<1)+(SDRAM_DW)
;REFRESH parameter
REFCYC EQU 858 ;period= 7.8us, HCLK=110Mhz, ( 7.8*110)
]
END
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