/* i82527.c - implementation of CAN Common Interface for Intel 82527 *//* Copyright 2001 Wind River Systems, Inc. *//* modification history --------------------05sep02,lsg modified for WindNet CAN 1,209nov01,dnb modified for integration into Tornado12jul01,jac written*//* DESCRIPTIONThis file contains the functions, specific to the Intel 82527 CANcontroller, that implement the interface defined in the wnCAN.h header file. *//* includes */#include <vxWorks.h>#include <errnoLib.h>#include <intLib.h>#include <iv.h>#include <sysLib.h>#include <CAN/wnCAN.h>#include <CAN/canController.h>#include <CAN/canBoard.h>#ifdef INCLUDE_I82527#include <CAN/i82527.h>#include <CAN/i82527Offsets.h>const WNCAN_ChannelType g_i82527chnType[I82527_MAX_MSG_OBJ] = {     WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_TRANSMIT_RECEIVE,    WNCAN_CHN_RECEIVE};/************************************************************************** I82527_Init - initialize the CAN controller** This function initializes the CAN controller and makes default selections.* 1. Puts the CAN controller into init mode* 2. Disables interrupts at the CAN controller level as well as channel level* 3. Sets bit timing values according to values stored in the CAN controller*    struct. If user has changed these values before init is called, the*    default bit timing values are set to a baud rate of 250K* 4. Sets local and global receive masks to don't care (accept all)* 5. Makes all channels inactive in hardware* 6. The CAN controller has now been initialized but will not participate*    in CAN bus communication. In order to bring the CAN controller online,*    and enable active participation in CAN bus activity, CAN_Start must*    be called following CAN_Init.** Call these functions in this order:* 1. CAN_Open* 2. CAN_Init* 3. CAN_Start** RETURNS: OK or ERROR** ERRNO:   S_can_busy**/static STATUS I82527_Init      (	  struct WNCAN_Device *pDev	  ){    UCHAR   value;    UINT    i;    STATUS  retCode = OK;	struct  i82527ChipSpecific *chipStuff;    if((pDev->pBrd->canInByte(pDev,I82527_R_INFR) & 0x80) != 0)    {        errnoSet(S_can_busy);        retCode = ERROR;    }    else        {        /* Set the default hardware reset state */        pDev->pBrd->canOutByte(pDev,I82527_R_INFR,0x61);		/*Disable interrupts and enbale configuration change*/        /*  set change configuration enable:         CCE  = 1            reset global interrupt enable:           IE   = 0            set init bit:                            Init = 1            disable error interrupt                  EEI  = 0            disable status change interrupt          SEI  = 0 */        pDev->pBrd->canOutByte(pDev, I82527_R_CTRL,0x41);        /* Reset Status Register */        pDev->pBrd->canOutByte(pDev, I82527_R_SR,0x07);		/* Set default values in chip specific struct*/		chipStuff = (struct i82527ChipSpecific *)pDev->pCtrl->csData;		chipStuff->busOffInt = FALSE;		chipStuff->wakeUpInt = FALSE;		chipStuff->errorInt = FALSE;    		                switch(pDev->pBrd->brdType)        {            case WNCAN_ESD_PC104_200:                /* set CLKOUT: 8 MHz < CLKOUT <= 16 MHz (SL1 = 1 SL0 = 0) */                pDev->pBrd->canOutByte(pDev, I82527_R_CLKO,0x20);                /* Comparator enabled, on TX1 RX1 connected */                pDev->pBrd->canOutByte(pDev, I82527_R_BCR,0x00);                /* SCLK = XTALl/2, MCLK = SYSCLK, CLKOUT disabled */                pDev->pBrd->canOutByte(pDev, I82527_R_INFR,0x40);                break;            case WNCAN_MSMCAN:                /* SCLK = XTALl/2, MCLK = SYSCLK, CLKOUT enabled */                pDev->pBrd->canOutByte(pDev, I82527_R_INFR,0x41);                /* set CLKOUT < 8 MHz */                pDev->pBrd->canOutByte(pDev, I82527_R_CLKO,0x30);                /* Comparator bypassed, RX1 disabled, RX0 enabled, TX1 enabled */                pDev->pBrd->canOutByte(pDev, I82527_R_BCR,0x42);                break;            default:                break;        }        /* Set default bit timing  */        value = (pDev->pCtrl->sjw << 6) | pDev->pCtrl->brp;        pDev->pBrd->canOutByte(pDev, I82527_R_BTR0 ,value);		if(pDev->pCtrl->samples)			value = 0x80 | (pDev->pCtrl->tseg2 << 4) | pDev->pCtrl->tseg1;		else			value = (pDev->pCtrl->tseg2 << 4) | pDev->pCtrl->tseg1;        pDev->pBrd->canOutByte(pDev, I82527_R_BTR1 ,value);		/* Set all message objects to invalid and reset each control register.		Set direction to transmit to prevent unwanted receive. */        for (i = 0;i < I82527_MAX_MSG_OBJ; i++)        {            pDev->pBrd->canOutByte(pDev, I82527_R_XMT+i*I82527_OFFS_MSG+                I82527_OFFS_CTRL0,0x55);            pDev->pBrd->canOutByte(pDev, I82527_R_XMT+i*I82527_OFFS_MSG+                I82527_OFFS_CTRL1,0x55);            pDev->pBrd->canOutByte(pDev, I82527_R_XMT+i*I82527_OFFS_MSG+                I82527_OFFS_MCR,0x08);        }		/* set message object 15 to 'don't care' */        pDev->pBrd->canOutByte(pDev, I82527_R_M15M,0);        pDev->pBrd->canOutByte(pDev, I82527_R_M15M+1,0);        pDev->pBrd->canOutByte(pDev, I82527_R_M15M+2,0);        pDev->pBrd->canOutByte(pDev, I82527_R_M15M+3,0);		        /* set global standard mask to 'don't care'*/        pDev->pBrd->canOutByte(pDev, I82527_R_GMS+0,0);        pDev->pBrd->canOutByte(pDev, I82527_R_GMS+1,0);		        /* set global extended mask to 'don't care'*/           pDev->pBrd->canOutByte(pDev, I82527_R_GME+0,0);        pDev->pBrd->canOutByte(pDev, I82527_R_GME+1,0);        pDev->pBrd->canOutByte(pDev, I82527_R_GME+2,0);        pDev->pBrd->canOutByte(pDev, I82527_R_GME+3,0);										        /* set all message objects to free */        for (i = 0; i < I82527_MAX_MSG_OBJ; i++)            pDev->pCtrl->chnMode[i] = WNCAN_CHN_INVALID;					        /*		 * leave the init bit set, clear the CCE bit to prevent write access		 * to configuration registers. The Init bit will be cleared and the		 * CAN controller brought online in CAN_Start		 */        pDev->pBrd->canOutByte(pDev, I82527_R_CTRL, 0x01);    }    return retCode;}/************************************************************************** I82527_Start - Put CAN controller online** This function is called to bring the CAN controller online. The CAN controller* can now participate in transmissions and receptions on the CAN bus.* This function must be called after CAN_Init has been called to initialize and* bring the CAN controller up in a known state.** RETURNS: N/A** ERRNO:   N/A**/void I82527_Start    (	struct WNCAN_Device *pDev	){	UCHAR value;			value = (pDev->pBrd->canInByte(pDev,I82527_R_CTRL));		/* Reset the Init bit */		value &= 0xfe;	    pDev->pBrd->canOutByte(pDev,I82527_R_CTRL,value);		return;	}/************************************************************************** I82527_Stop - Put CAN controller offline** Disables communication between CAN controller and the CAN bus** RETURNS: N/A*   * ERRNO:   N/A**/void I82527_Stop    (	struct WNCAN_Device *pDev	){	UCHAR value;			value = (pDev->pBrd->canInByte(pDev,I82527_R_CTRL));		/* Set the Init bit */		value |= 0x01;	    pDev->pBrd->canOutByte(pDev,I82527_R_CTRL,value);		return;	}/************************************************************************** I82527_SetBitTiming - set bit timing** This function sets the baud rate of the controller. The selection* of the input parameters should be based on an established set of * recommendations for the particular application.* This function sets the bit timing values in the hardware as well as the* controller structure, so that the bit timing values are not lost if Init* is called again. The function will preserve the state of the CAN controller.* i.e. if the CAN controller is online when the function is called, then the * CAN controller will be online when the function exits. ** bit time = 1 + (tseg1 + 1) + (tseg2+1) time quanta * The interpretation of tseg1 are tseg2 are according to the controller's * definition and hence can be written to directly using this function.** In all cases so far, tseg2 refers to the segment of bit time after the sample* point. However, in some controllers tseg1 refers to the segment of bit time* after the end of sync seg upto the sample point.                     *  ---------------------------------------------------------* |    |                    |                              |  *  sync <--------tseg1 --->^|^<---------tseg2 ------------->*                          sample point * ** RETURNS: OK, or ERROR** ERRNO:   S_can_invalid_parameter***/static STATUS I82527_SetBitTiming      (	  struct WNCAN_Device *pDev,	  UCHAR tseg1, 	  UCHAR tseg2, 	  UCHAR brp, 	  UCHAR sjw,	  BOOL  samples	  ){    UCHAR       value;    STATUS      retCode;	    retCode = OK;  /* assume success */	    /* qualify parameters */    if((sjw > 0x03) || (brp > 0x3f) || (tseg1 > 15) ||		(tseg1 < 2) || (tseg2 > 7) || (tseg2 < 1))    {        errnoSet(S_can_invalid_parameter);        retCode = ERROR;    }    else    { 							/* Check if init and configuration change enable bits are set */        /* if not set both */        value = pDev->pBrd->canInByte(pDev, I82527_R_CTRL);				if((value & 0x41) != 0x41)			pDev->pBrd->canOutByte(pDev, I82527_R_CTRL, (value | 0x41));                pDev->pBrd->canOutByte(pDev, I82527_R_BTR0, (sjw << 6) | brp);				if(samples)			pDev->pBrd->canOutByte(pDev, I82527_R_BTR1, (0x80 | (tseg2 << 4) | tseg1));					else			pDev->pBrd->canOutByte(pDev, I82527_R_BTR1, ((tseg2 << 4) | tseg1));						/*restore original state of controller*/		if((value & 0x41) != 0x41)			pDev->pBrd->canOutByte(pDev, I82527_R_CTRL, value);		    }	    return retCode;}/**************************************************************************** I82527_GetBaudRate: Returns baud rate by recalculating bit timing parameters* * RETURNS: baud rate in bps* * ERRNO:   N/A*/static UINT I82527_GetBaudRate      (      struct WNCAN_Device *pDev,	  UINT *samplePoint      ){           	ULONG             sys_clk_frequency;    USHORT            num_time_quanta;    UCHAR             brp, tseg1, tseg2, btr1, value;                    brp = (pDev->pBrd->canInByte(pDev, I82527_R_BTR0) & 0x3f) + 1;        btr1 = pDev->pBrd->canInByte(pDev, I82527_R_BTR1);          tseg2 = ((btr1 & 0x70) >> 4) + 1;    tseg1 = (btr1 & 0x0f) + 1;                     /*Calculate baud rate*/    num_time_quanta = 1 + tseg1 + tseg2;	/* Check the DSC bit in the CPU Interface register */	value = pDev->pBrd->canInByte(pDev, I82527_R_INFR);	if(value & I82527_B_DSC)		sys_clk_frequency = pDev->pBrd->xtalFreq / 2;	else		sys_clk_frequency = pDev->pBrd->xtalFreq;    *samplePoint = ((1 + tseg1) * 100)/num_time_quanta;    return(sys_clk_frequency / (num_time_quanta * brp));}/************************************************************************** I82527_SetIntMask - enable controller level interrupts on the CAN*                     controller** This function enables the specified list of controller level interrupts* on the CAN controller. Interrupts are not enabled at the CAN board level* or at the CPU level.** The interrupt masks available are:* WNCAN_INT_ERROR : enables interrupt on bit error* WNCAN_INT_WAKE_UP: enables interrupt on wake up* Bit errors and wake from sleep mode, are signalled as status change* interrupts on the I82527. Setting the status change interrupt enable bit* corresponds to  enabling WCAN_INT_ERROR and WNCAN_INT_WAKE_UP * CAN_GetIntStatus will return the cause of the status change interrupt, * and this information will be passed on to the user's ISR call back routine* when an interrupt occurs.** WARNING* However, successful transmissions and receptions are also status changes* and will trigger the status change interrupt if enabled. This will greatly * burden the CPU.** WNCAN_INT_BUS_OFF: enables interrupt indicating bus off condition  * The Error Interrupt Enable (EIE) bit in the control register, enables * an interrupt to occur when the error status of the I82527 changes. Error * interrupts are Bus Off and Warn in the staus register.* To enable WNCAN_INT_BUS_OFF, EIE is set. When an interrupt corresponding to* this condition occurs, CAN_GetIntStatus identifies the interrupt source* and * * RETURNS: OK** ERRNO:   S_can_invalid_parameter**/static STATUS I82527_SetIntMask      (	  struct WNCAN_Device *pDev,	  WNCAN_IntType intMask	  ){        STATUS   retCode=OK;        int         oldLevel;	struct  i82527ChipSpecific *chipStuff;	UCHAR   regCtrl;	/*        return error if masks other than error, busoff and wakeup        are passed to the function        */        if((intMask > (WNCAN_INT_ERROR | WNCAN_INT_BUS_OFF | WNCAN_INT_WAKE_UP)) &&           (intMask != WNCAN_INT_ALL)) 	{           errnoSet(S_can_invalid_parameter);           retCode = ERROR;                }        else        {	/* Set default values in chip specific struct*/	chipStuff = (struct i82527ChipSpecific *)pDev->pCtrl->csData;	       /* read the control register */       regCtrl = pDev->pBrd->canInByte(pDev, I82527_R_CTRL);		/*Enable all error interrupts. Bus error,  data overrun*/	if(intMask & WNCAN_INT_ERROR) 		chipStuff->errorInt = TRUE;			else