/******************************************************************************\*           Copyright (C) 2000 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_pcihal.h* DATE CREATED.. 10/02/2000* LAST MODIFIED. 08/02/2004 - Adding support for C6418*                06/09/2003*------------------------------------------------------------------------------* REGISTERS**   RSTSRC   - Reset Source/Status register*   PMDCSR   - Power Management DSP Control/Status register*   PCIIS    - PCI Interrupt Source register*   PCIIEN   - PCI Interrupt Enable register*   DSPMA    - DSP Master Address register*   PCIMA    - PCI Master Address register*   PCIMC    - PCI Master Control register*   CDSPA    - Current DSP Address register*   CPCIA    - Current PCI Address regsiter*   CCNT     - Current Byte Count register*   HALT     - PCI Transfer Halt register (1)*   EEADD    - EEPROM Address register*   EEDAT    - EEPROM Date register*   EECTL    - EEPROM Control register*   TRCTL    - Transfer request control register(C64x Only)**   (1) not supported by C64x devices\******************************************************************************/#ifndef _CSL_PCIHAL_H_#define _CSL_PCIHAL_H_#include <csl_stdinc.h>#if (PCI_SUPPORT)/******************************************************************************\* MISC section\******************************************************************************/#if (C64_SUPPORT)  #define _PCI_BASE1_GLOBAL             0x01C00000u  #define _PCI_BASE2_GLOBAL             0x01C20000u  #define _PCI_BASE3_GLOBAL             0x01C30000u#else  #define _PCI_BASE1_GLOBAL             0x01A40000u  #define _PCI_BASE2_GLOBAL             0x01A80000u#endif/******************************************************************************\* module level register/field access macros\******************************************************************************/  /* ----------------- */  /* FIELD MAKE MACROS */  /* ----------------- */  #define PCI_FMK(REG,FIELD,x)\    _PER_FMK(DMA,##REG,##FIELD,x)  #define PCI_FMKS(REG,FIELD,SYM)\    _PER_FMKS(DMA,##REG,##FIELD,##SYM)  /* -------------------------------- */  /* RAW REGISTER/FIELD ACCESS MACROS */  /* -------------------------------- */  #define PCI_ADDR(REG)\    _PCI_##REG##_ADDR  #define PCI_RGET(REG)\    _PER_RGET(_PCI_##REG##_ADDR,PCI,##REG)  #define PCI_RSET(REG,x)\    _PER_RSET(_PCI_##REG##_ADDR,PCI,##REG,x)  #define PCI_FGET(REG,FIELD)\    _PCI_##REG##_FGET(##FIELD)  #define PCI_FSET(REG,FIELD,x)\    _PCI_##REG##_FSET(##FIELD,##x)  #define PCI_FSETS(REG,FIELD,SYM)\    _PCI_##REG##_FSETS(##FIELD,##SYM)  /* ------------------------------------------ */  /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */  /* ------------------------------------------ */  #define PCI_RGETA(addr,REG)\    _PER_RGET(addr,PCI,##REG)  #define PCI_RSETA(addr,REG,x)\    _PER_RSET(addr,PCI,##REG,x)  #define PCI_FGETA(addr,REG,FIELD)\    _PER_FGET(addr,PCI,##REG,##FIELD)  #define PCI_FSETA(addr,REG,FIELD,x)\    _PER_FSET(addr,PCI,##REG,##FIELD,x)  #define PCI_FSETSA(addr,REG,FIELD,SYM)\    _PER_FSETS(addr,PCI,##REG,##FIELD,##SYM)/******************************************************************************\* _____________________* |                   |* |  R S T S R C      |* |___________________|** RSTSRC - DSP Reset Source-Status Regsiter** FIELDS (msb -> lsb)* (r)  CFGERR* (r)  CFGDONE* (w)  INTRST* (w)  INTREQ* (r)  WARMRST* (r)  PRST* (r)  RST*\******************************************************************************/  #define _PCI_RSTSRC_OFFSET      0  #if (C64_SUPPORT)  #define _PCI_RSTSRC_ADDR        0x01C00000u  #else  #define _PCI_RSTSRC_ADDR        0x01A40000u  #endif  #define _PCI_RSTSRC_CFGERR_MASK         0x00000040u  #define _PCI_RSTSRC_CFGERR_SHIFT        0x00000006u  #define  PCI_RSTSRC_CFGERR_DEFAULT      0x00000000u  #define  PCI_RSTSRC_CFGERR_OF(x)        _VALUEOF(x)  #define _PCI_RSTSRC_CFGDONE_MASK        0x00000020u  #define _PCI_RSTSRC_CFGDONE_SHIFT       0x00000005u  #define  PCI_RSTSRC_CFGDONE_DEFAULT     0x00000000u  #define  PCI_RSTSRC_CFGDONE_OF(x)       _VALUEOF(x)  #define _PCI_RSTSRC_INTRST_MASK         0x00000010u  #define _PCI_RSTSRC_INTRST_SHIFT        0x00000004u  #define  PCI_RSTSRC_INTRST_DEFAULT      0x00000000u  #define  PCI_RSTSRC_INTRST_OF(x)        _VALUEOF(x)  #define  PCI_RSTSRC_INTRST_YES          0x00000001u  #define  PCI_RSTSRC_INTRST_NO           0x00000000u  #define _PCI_RSTSRC_INTREQ_MASK         0x00000008u  #define _PCI_RSTSRC_INTREQ_SHIFT        0x00000003u  #define  PCI_RSTSRC_INTREQ_DEFAULT      0x00000000u  #define  PCI_RSTSRC_INTREQ_OF(x)        _VALUEOF(x)  #define  PCI_RSTSRC_INTREQ_YES          0x00000001u  #define  PCI_RSTSRC_INTREQ_NO           0x00000000u  #define _PCI_RSTSRC_WARMRST_MASK        0x00000004u  #define _PCI_RSTSRC_WARMRST_SHIFT       0x00000002u  #define  PCI_RSTSRC_WARMRST_DEFAULT     0x00000000u  #define  PCI_RSTSRC_WARMRST_OF(x)        _VALUEOF(x)  #define _PCI_RSTSRC_PRST_MASK           0x00000002u  #define _PCI_RSTSRC_PRST_SHIFT          0x00000001u  #define  PCI_RSTSRC_PRST_DEFAULT        0x00000000u  #define  PCI_RSTSRC_PRST_OF(x)		_VALUEOF(x)  #define _PCI_RSTSRC_RST_MASK            0x00000001u  #define _PCI_RSTSRC_RST_SHIFT        	0x00000000u  #define  PCI_RSTSRC_RST_DEFAULT       	0x00000001u  #define  PCI_RSTSRC_RST_OF(x)           _VALUEOF(x)  #define  PCI_RSTSRC_OF(x)              _VALUEOF(x)  #define PCI_RSTRC_DEFAULT (Uint32)( \     _PER_FDEFAULT(PCI,RSTSRC,CFGERR) \    |_PER_FDEFAULT(PCI,RSTSRC,CFGDONE) \    |_PER_FDEFAULT(PCI,RSTSRC,INTRST) \    |_PER_FDEFAULT(PCI,RSTSRC,INTREQ) \    |_PER_FDEFAULT(PCI,RSTSRC,WARMRST) \    |_PER_FDEFAULT(PCI,RSTSRC,PRST) \    |_PER_FDEFAULT(PCI,RSTSRC,RST) \   )  #define PCI_RSTSRC_RMK(intrst,intreq) \    (Uint32)( \     _PER_FMK(PCI,RSTSRC,INTRST,intrst) \    |_PER_FMK(PCI,RSTSRC,INTREQ,intreq) \   ) #define _PCI_RSTSRC_FGET(FIELD)\    _PER_FGET(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD) #define _PCI_RSTSRC_FSET(FIELD,field)\    _PER_FSET(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD,field) #define _PCI_RSTSRC_FSETS(FIELD,SYM)\    _PER_FSETS(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD,##SYM)/******************************************************************************\* _____________________* |                   |* |  P M D C S R      |* |___________________|** PMDCSR - Power Management DSP Control-Status Register** FIELDS (msb -> lsb)* (rw) HWPMECTL* (r)  D3WARMONWKP* (r)  D2WARMONWKP* (rw) PMEEN* (r)  PWRWKP* (rw) PMESTAT* (r)  PMEDRVN* (r)  AUXDETECT* (rw) CURSTATE* (r)  REQSTATE*\******************************************************************************/  #define _PCI_PMDCSR_OFFSET      1 #if (C64_SUPPORT)  #define _PCI_PMDCSR_ADDR                0x01C00004u #else  #define _PCI_PMDCSR_ADDR                0x01A40004u #endif  #define _PCI_PMDCSR_HWPMECTL_MASK          0x0007F800u  #define _PCI_PMDCSR_HWPMECTL_SHIFT         0x0000000Bu  #define  PCI_PMDCSR_HWPMECTL_DEFAULT       0x00000088u  #define  PCI_PMDCSR_HWPMECTL_OF(x)         _VALUEOF(x)  #define  PCI_PMDCSR_HWPMECTL_REQD0         0x00000001u  #define  PCI_PMDCSR_HWPMECTL_REQD1         0x00000002u  #define  PCI_PMDCSR_HWPMECTL_REQD2         0x00000003u  #define  PCI_PMDCSR_HWPMECTL_REQD3         0x00000004u  #define _PCI_PMDCSR_D3WARMONWKP_MASK       0x00000400u  #define _PCI_PMDCSR_D3WARMONWKP_SHIFT      0x0000000Au  #define  PCI_PMDCSR_D3WARMONWKP_DEFAULT    0x00000000u  #define  PCI_PMDCSR_D3WARMONWKP_OF(x)      _VALUEOF(x)  #define _PCI_PMDCSR_D2WARMONWKP_MASK       0x00000200u  #define _PCI_PMDCSR_D2WARMONWKP_SHIFT      0x00000009u  #define  PCI_PMDCSR_D2WARMONWKP_DEFAULT    0x00000000u  #define  PCI_PMDCSR_D2WARMONWKP_OF(x)     _VALUEOF(x)  #define _PCI_PMDCSR_PMEEN_MASK            0x00000100u  #define _PCI_PMDCSR_PMEEN_SHIFT           0x00000008u  #define  PCI_PMDCSR_PMEEN_DEFAULT         0x00000000u  #define  PCI_PMDCSR_PMEEN_OF(x)           _VALUEOF(x)  #define  PCI_PMDCSR_PMEEN_CLR             0x00000001u  #define _PCI_PMDCSR_PMEWKP_MASK            0x00000080u  #define _PCI_PMDCSR_PMEWKP_SHIFT           0x00000007u  #define  PCI_PMDCSR_PMEWKP_DEFAULT         0x00000000u  #define  PCI_PMDCSR_PMEWKP_OF(x)           _VALUEOF(x)  #define _PCI_PMDCSR_PMESTAT_MASK           0x00000040u  #define _PCI_PMDCSR_PMESTAT_SHIFT          0x00000006u  #define  PCI_PMDCSR_PMESTAT_DEFAULT        0x00000000u  #define  PCI_PMDCSR_PMESTAT_OF(x)          _VALUEOF(x)  #define  PCI_PMDCSR_PMESTAT_SET            0x00000001u  #define _PCI_PMDCSR_PMEDRVN_MASK           0x00000020u  #define _PCI_PMDCSR_PMEDRVN_SHIFT          0x00000005u  #define  PCI_PMDCSR_PMEDRVN_DEFAULT        0x00000000u  #define  PCI_PMDCSR_PMEDRVN_OF(x)          _VALUEOF(x)  #define _PCI_PMDCSR_AUXDETECT_MASK         0x00000010u  #define _PCI_PMDCSR_AUXDETECT_SHIFT        0x00000004u  #define  PCI_PMDCSR_AUXDETECT_DEFAULT      0x00000000u  #define  PCI_PMDCSR_AUXDETECT_OF(x)          _VALUEOF(x)  #define _PCI_PMDCSR_CURSTATE_MASK          0x0000000Cu  #define _PCI_PMDCSR_CURSTATE_SHIFT         0x00000002u  #define  PCI_PMDCSR_CURSTATE_DEFAULT       0x00000000u  #define  PCI_PMDCSR_CURSTATE_OF(x)         _VALUEOF(x)  #define  PCI_PMDCSR_CURSTATE_D0            0x00000000u  #define  PCI_PMDCSR_CURSTATE_D1	    	   0x00000001u  #define  PCI_PMDCSR_CURSTATE_D2            0x00000002u  #define  PCI_PMDCSR_CURSTATE_D3            0x00000003u  #define _PCI_PMDCSR_REQSTATE_MASK          0x00000003u  #define _PCI_PMDCSR_REQSTATE_SHIFT         0x00000000u  #define  PCI_PMDCSR_REQSTATE_DEFAULT       0x00000000u  #define  PCI_PMDCSR_REQSTATE_OF(x)         _VALUEOF(x)  #define  PCI_PMDCSR_OF(x)                  _VALUEOF(x) #define PCI_PMDCSR_DEFAULT (Uint32)( \     _PER_FDEFAULT(PCI,PMDCSR,HWPMECTL) \    |_PER_FMK(PCI,PMDCSR,D3WARMONWKP) \    |_PER_FMK(PCI,PMDCSR,D2WARMONWKP) \    |_PER_FDEFAULT(PCI,PMDCSR,PMEEN) \    |_PER_FDEFAULT(PCI,PMDCSR,PMEWKP) \    |_PER_FDEFAULT(PCI,PMDCSR,PMESTAT) \    |_PER_FDEFAULT(PCI,PMDCSR,PMEDRVN) \    |_PER_FDEFAULT(PCI,PMDCSR,AUXDETECT) \    |_PER_FDEFAULT(PCI,PMDCSR,CURSTATE) \    |_PER_FDEFAULT(PCI,PMDCSR,REQSTATE) \   )  #define PCI_PMDCSR_RMK(hwpmectl,pmeen,pmestat,curstate) \    (Uint32)( \     _PER_FMK(PCI,PMDCSR,HWPMECTL,hwpmectl) \    |_PER_FMK(PCI,PMDCSR,PMEEN,pmeena) \    |_PER_FMK(PCI,PMDCSR,PMESTAT,pmestat) \    |_PER_FMK(PCI,PMDCSR,CURSTATE,curstate) \   ) #define _PCI_PMDCSR_FGET(FIELD)\    _PER_FGET(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD) #define _PCI_PMDCSR_FSET(FIELD,field)\    _PER_FSET(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD,field) #define _PCI_PMDCSR_FSETS(FIELD,SYM)\    _PER_FSETS(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD,##SYM)/******************************************************************************\* _____________________* |                   |* |  P C I I S        |* |___________________|** PCIIS - PCI Interrupt Source Register** FIELDS (msb -> lsb)* (rw) DMAHALTED* (rw) PRST* (rw) EERDY* (rw) CFGERR* (rw) CFGDONE* (rw) MASTEROK* (rw) PWRHL* (rw) PWRLH* (rw) HOSTSW* (rw) PCIMASTER* (rw) PCITARGET* (rw) PWRMGMT*\******************************************************************************/  #define _PCI_PCIIS_OFFSET     2 #if (C64_SUPPORT)   #define _PCI_PCIIS_ADDR                0x01C00008u #else   #define _PCI_PCIIS_ADDR                0x01A40008u #endif  #define _PCI_PCIIS_DMAHALTED_MASK         0x00001000u  #define _PCI_PCIIS_DMAHALTED_SHIFT        0x0000000Cu  #define  PCI_PCIIS_DMAHALTED_DEFAULT      0x00000000u  #define  PCI_PCIIS_DMAHALTED_OF(x)        _VALUEOF(x)  #define  PCI_PCIIS_DMAHALTED_CLR          0x00000001u  #define _PCI_PCIIS_PRST_MASK              0x00000800u  #define _PCI_PCIIS_PRST_SHIFT             0x0000000Bu  #define  PCI_PCIIS_PRST_DEFAULT           0x00000000u  #define  PCI_PCIIS_PRST_OF(x)             _VALUEOF(x)  #define  PCI_PCIIS_PRST_CHGSTATE          0x00000001u  #define  PCI_PCIIS_PRST_NOCHG             0x00000000u  #define _PCI_PCIIS_EERDY_MASK             0x00000200u  #define _PCI_PCIIS_EERDY_SHIFT            0x00000009u  #define  PCI_PCIIS_EERDY_DEFAULT          0x00000000u  #define  PCI_PCIIS_EERDY_OF(x)            _VALUEOF(x)  #define  PCI_PCIIS_EERDY_CLR              0x00000001u  #define _PCI_PCIIS_CFGERR_MASK            0x00000100u  #define _PCI_PCIIS_CFGERR_SHIFT          0x00000008u  #define  PCI_PCIIS_CFGERR_DEFAULT         0x00000000u  #define  PCI_PCIIS_CFGERR_OF(x)           _VALUEOF(x)  #define  PCI_PCIIS_CFGERR_CLR             0x00000001u  #define _PCI_PCIIS_CFGDONE_MASK           0x00000080u  #define _PCI_PCIIS_CFGDONE_SHIFT          0x00000007u  #define  PCI_PCIIS_CFGDONE_DEFAULT        0x00000000u  #define  PCI_PCIIS_CFGDONE_OF(x)          _VALUEOF(x)  #define  PCI_PCIIS_CFGDONE_CLR            0x00000001u  #define _PCI_PCIIS_MASTEROK_MASK          0x00000040u  #define _PCI_PCIIS_MASTEROK_SHIFT         0x00000006u  #define  PCI_PCIIS_MASTEROK_DEFAULT       0x00000000u  #define  PCI_PCIIS_MASTEROK_OF(x)         _VALUEOF(x)  #define  PCI_PCIIS_MASTEROK_CLR           0x00000001u  #define _PCI_PCIIS_PWRHL_MASK             0x00000020u  #define _PCI_PCIIS_PWRHL_SHIFT            0x00000005u  #define  PCI_PCIIS_PWRHL_DEFAULT          0x00000000u  #define  PCI_PCIIS_PWRHL_OF(x)            _VALUEOF(x)  #define  PCI_PCIIS_PWRHL_CLR              0x00000001u  #define _PCI_PCIIS_PWRLH_MASK             0x00000010u  #define _PCI_PCIIS_PWRLH_SHIFT            0x00000004u  #define  PCI_PCIIS_PWRLH_DEFAULT          0x00000000u  #define  PCI_PCIIS_PWRLH_OF(x)            _VALUEOF(x)  #define  PCI_PCIIS_PWRLH_CLR              0x00000001u  #define _PCI_PCIIS_HOSTSW_MASK            0x00000008u