?? csl_legacyhal.h
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/*
* Copyright 2001 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.60.22 12-07-01 (barracuda-j15)" */
/******************************************************************************\
* Copyright (C) 2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_legacyhal.h
* DATE CREATED.. 09/01/2000
* LAST MODIFIED. 03/08/2002
\******************************************************************************/
#ifndef _CSL_LEGACYHAL_H_
#define _CSL_LEGACYHAL_H_
#include "csl_stdinc.h"
#include "csl_chiphal.h"
/*----------------------------------------------------------------------------*/
/* Legacy HAL support macro definitions */
/*----------------------------------------------------------------------------*/
#define _VALUEOF(x) ((Uint32)(x))
#ifndef UNREFERENCED_PARAMETER
#define UNREFERENCED_PARAMETER(P) ((P)=(P))
#endif
#ifndef REG32
#define REG32(addr) (*(volatile unsigned int*)(addr))
#define REG16(addr) (*(volatile unsigned short*)(addr))
#define REG8(addr) (*(volatile unsigned char*)(addr))
#endif
/* memory mapped register macros */
#define HFIELD_GET(RegAddr,FIELD) (Uint32)( \
(REG32(RegAddr)&##FIELD##_MASK)>>##FIELD##_SHIFT \
)
#define HFIELD_SET(RegAddr,FIELD,Val) REG32(RegAddr)=(Uint32)( \
(REG32(RegAddr)&~##FIELD##_MASK)| \
(((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \
)
#define HFIELD_SHIFT(FIELD,Val) \
(((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK)
#define HREG32_GET(RegAddr) \
(Uint32)REG32(RegAddr)
#define HREG32_SET(RegAddr,Val) \
REG32(RegAddr)=(Uint32)(Val)
/* control register macros */
#define HCRFIELD_GET(CRREG,FIELD) (Uint32)( \
(((CRREG)&##FIELD##_MASK)>>##FIELD##_SHIFT) \
)
#define HCRFIELD_SET(CRREG,FIELD,Val) CRREG = (Uint32)( \
((CRREG)&~##FIELD##_MASK)| \
(((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \
)
#define HCRFIELD_SHIFT(FIELD,Val) \
(((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK)
#define HCRREG32_GET(CRREG) \
(Uint32)(CRREG)
#define HCRREG32_SET(CRREG,Val) \
(CRREG)=(Uint32)(Val)
/******************************************************************************\
* Copyright (C) 1999-2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... chiphal.h
* DATE CREATED.. 08/19/1999
* LAST MODIFIED. 03/08/2000
*
*------------------------------------------------------------------------------
* DESCRIPTION: (HAL interface file for the CHIP module)
*
* CHIP Control Registers Covered
* HCHIP_CSR - control status register
* HCHIP_IFR - interrupt flag register
* HCHIP_ISR - interrupt set register
* HCHIP_ICR - interrupt clear register
* HCHIP_IER - interrupt enable register
* HCHIP_ISTP - interrupt service table pointer
* HCHIP_IRP - interrrupt return pointer
* HCHIP_NRP - nonmaskable interrupt return pointer
* HCHIP_AMR - addressing mode register
* HCHIP_FADCR - floating-point adder config register (1)
* HCHIP_FAUCR - floating-point auxiliary config register (1)
* HCHIP_FMCR - floating-point multiplier config register (1)
*
* (1) only on devices with an FPU
*
\******************************************************************************/
#ifndef _CHIPHAL_H_
#define _CHIPHAL_H_
/*----------------------------------------------------------------*/
#define HCHIP_PERBASE_ADDR (0x01800000)
/******************************************************************************\
* HCHIP_NULL - dummy register
*
\******************************************************************************/
#define HCHIP_NULL_ADDR ((UINT32)(0x01840074))
#define HCHIP_NULL REG32(HCHIP_NULL_ADDR)
/******************************************************************************\
* HCHIP_CSR - control status register
*
* Fields:
* (RW) HCHIP_CSR_GIE
* (RW) HCHIP_CSR_PGIE
* (RW) HCHIP_CSR_DCC
* (RW) HCHIP_CSR_PCC
* (R) HCHIP_CSR_EN
* (RC) HCHIP_CSR_SAT
* (RW) HCHIP_CSR_PWRD
* (R) HCHIP_CSR_REVID
* (R) HCHIP_CSR_CPUID
*
\******************************************************************************/
extern far cregister volatile unsigned int CSR;
#define HCHIP_CSR CSR
/*----------------------------------------------------------------------------*\
* (RW) HCHIP_CSR_GIE
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_GIE_MASK (0x00000001)
#define HCHIP_CSR_GIE_SHIFT (0x00000000)
#define HCHIP_CSR_GIE_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_GIE)
#define HCHIP_CSR_GIE_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_GIE,Val)
/*----------------------------------------------------------------------------*\
* (RW) HCHIP_CSR_PGIE
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_PGIE_MASK (0x00000002)
#define HCHIP_CSR_PGIE_SHIFT (0x00000001)
#define HCHIP_CSR_PGIE_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_PGIE)
#define HCHIP_CSR_PGIE_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_PGIE,Val)
/*----------------------------------------------------------------------------*\
* (RW) HCHIP_CSR_DCC
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_DCC_MASK (0x0000001C)
#define HCHIP_CSR_DCC_SHIFT (0x00000002)
#define HCHIP_CSR_DCC_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_DCC)
#define HCHIP_CSR_DCC_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_DCC,Val)
/*----------------------------------------------------------------------------*\
* (RW) HCHIP_CSR_PCC
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_PCC_MASK (0x000000E0)
#define HCHIP_CSR_PCC_SHIFT (0x00000005)
#define HCHIP_CSR_PCC_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_PCC)
#define HCHIP_CSR_PCC_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_PCC,Val)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_CSR_EN
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_EN_MASK (0x00000100)
#define HCHIP_CSR_EN_SHIFT (0x00000008)
#define HCHIP_CSR_EN_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_EN)
/*----------------------------------------------------------------------------*\
* (RC) HCHIP_CSR_SAT
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_SAT_MASK (0x00000200)
#define HCHIP_CSR_SAT_SHIFT (0x00000009)
#define HCHIP_CSR_SAT_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_SAT)
#define HCHIP_CSR_SAT_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_SAT,Val)
/*----------------------------------------------------------------------------*\
* (W) HCHIP_CSR_PWRD
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_PWRD_MASK (0x0000FC00)
#define HCHIP_CSR_PWRD_SHIFT (0x0000000A)
#define HCHIP_CSR_PWRD_SET(CrReg,Val) \
HCRFIELD_SET(CrReg,HCHIP_CSR_PWRD,Val)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_CSR_REVID
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_REVID_MASK (0x00FF0000)
#define HCHIP_CSR_REVID_SHIFT (0x00000010)
#define HCHIP_CSR_REVID_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_REVID)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_CSR_CPUID
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_CPUID_MASK (0xFF000000)
#define HCHIP_CSR_CPUID_SHIFT (0x00000018)
#define HCHIP_CSR_CPUID_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_CSR_CPUID)
/*----------------------------------------------------------------------------*\
* (RW) HCHIP_CSR
\*----------------------------------------------------------------------------*/
#define HCHIP_CSR_GET(CrReg) HCRREG32_GET(CrReg)
#define HCHIP_CSR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)
#define HCHIP_CSR_CFG(CrReg,gie,pgie,dcc,pcc,pwrd) CrReg=(UINT32)( \
HCRFIELD_SHIFT(HCHIP_CSR_GIE, gie) |\
HCRFIELD_SHIFT(HCHIP_CSR_PGIE,pgie)|\
HCRFIELD_SHIFT(HCHIP_CSR_DCC, dcc) |\
HCRFIELD_SHIFT(HCHIP_CSR_PCC, pcc) |\
HCRFIELD_SHIFT(HCHIP_CSR_PWRD,pwrd) \
)
/******************************************************************************\
* HCHIP_IFR - interrupt flag register
*
* Fields:
* (R) HCHIP_IFR_NMIF
* (R) HCHIP_IFR_IF4
* (R) HCHIP_IFR_IF5
* (R) HCHIP_IFR_IF6
* (R) HCHIP_IFR_IF7
* (R) HCHIP_IFR_IF8
* (R) HCHIP_IFR_IF9
* (R) HCHIP_IFR_IF10
* (R) HCHIP_IFR_IF11
* (R) HCHIP_IFR_IF12
* (R) HCHIP_IFR_IF13
* (R) HCHIP_IFR_IF14
* (R) HCHIP_IFR_IF15
*
\******************************************************************************/
extern far cregister volatile unsigned int IFR;
#define HCHIP_IFR IFR
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_NMIF
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_NMIF_MASK (0x00000002)
#define HCHIP_IFR_NMIF_SHIFT (0x00000001)
#define HCHIP_IFR_NMIF_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_NMIF)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF4
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_IF4_MASK (0x00000010)
#define HCHIP_IFR_IF4_SHIFT (0x00000004)
#define HCHIP_IFR_IF4_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_IF4)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF5
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_IF5_MASK (0x00000020)
#define HCHIP_IFR_IF5_SHIFT (0x00000005)
#define HCHIP_IFR_IF5_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_IF5)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF6
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_IF6_MASK (0x00000040)
#define HCHIP_IFR_IF6_SHIFT (0x00000006)
#define HCHIP_IFR_IF6_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_IF6)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF7
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_IF7_MASK (0x00000080)
#define HCHIP_IFR_IF7_SHIFT (0x00000007)
#define HCHIP_IFR_IF7_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_IF7)
/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF8
\*----------------------------------------------------------------------------*/
#define HCHIP_IFR_IF8_MASK (0x00000100)
#define HCHIP_IFR_IF8_SHIFT (0x00000008)
#define HCHIP_IFR_IF8_GET(CrReg) \
HCRFIELD_GET(CrReg,HCHIP_IFR_IF8)
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