/******************************************************************************\* Step 1.     Copyright (C) 2001 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_mcasphal.h* DATE CREATED.. 06/28/2001 * LAST MODIFIED. *                08/02/2004 - Adding support for C6418*------------------------------------------------------------------------------*HISTORY......6/29/01, changed RSLOT to RSLOTCNT, XSLOT to XSLOTCNT* 7/2/01, XFMT: changed XROT field to 0-2 instead of 0-3*	also added field XDATDLY in bits 17:16 (made appropriate macro changes)*	RFMT: same as above (RROT wasn't specified, but made sense)*	AFSXCTL/AFSRCTL: removed X(R)DATDLY fields and macro entries.*	ACLKRCTL: changed CLKRDIV field to bits 4:0(was 5:0),CLKRM to bit 5(was 6)*	HCLKXDIV/HCLKRDIV: changed field HCLKX(R)DIV to bit 11:0 (was 12:0)*	SCRTL: changed defaults of fields XRDY and RRDY to 0b (was 1b)*	Added register DLBCTL*	Added registers X(R)INTCTL*	8/6/01 fixed MCASP_RFMT_RPAD_RPBIT; was formerly _XPBIT*	08/13/01  V.G.  Reordered the registers and added OFFSETs*	08/14/01  V.G.  Corrected syntax errors*	08/20/01  V.G.	Added addresses for each register**     17/06/04        Adding support for DM640/641*     11/03/01  F.S   CRFAIL -> RCKFAIL / CXFAIL -> XCKFAIL*     11/15/01  F.S   PWREMUMGT -> PWRDEMU*                     PFUNC / PDIR /PDSOUT /PDSET /PDCLR -> fields renaming*     11/20/01  F.S   GBLCTL / XGBLCTL / RGBLCTL *                     RRST -> RSMRST , RGRST -> RCLKRST , HCLKRRST -> RHCLKRST*                     XRST -> XSMRST , XGRST -> XCLKRST , HCLKXRST -> XHCLKRST*     10/22/03        Fixed the typos in MCASP_PDOUT_DEFAULT and MCASP_PDOUT_RMK*                            *------------------------------------------------------------------------------* REGISTERS (register list)** PID		- Peripheral Identification Register            * PWRDEMU	- Power Down and Emulation Management Register  * PFUNC		- Pin Function / GPIO Enable Register  * PDIR		- Pin Direction Register * PDAT		- Pin Data Register   * PDIN		- Pin Data Input Register  * PDOUT		- Pin Data Output Register  * PDSET		- Pin Data Set Register * PDCLR		- Pin Data Clear Register  * DITCTL    - Transmit DIT Control Register  * DLBCTL    -  Loop Back Control Mode* XFMT		- Transmit Bitstream Format Register * RFMT		- Receive Bitstream Format Register  * XMASK* RMASK		* AFSXCTL	- Transmit Frame Control Register * AFSRCTL	- Receive Frame Control Register * ACLKXCTL	- Transmit Clock Control Register * ACLKRCTL	- Receive Clock Control Register * AHCLKXCTL	- High Frequency Transmit Clock Control Register Description* AHCLKRCTL	- High Frequency Receive Clock Control Register Description     * SRCTL0	- Serializer Control Register 0* SRCTL1	- Serializer Control Register 1* SRCTL2	- Serializer Control Register 2* SRCTL3	- Serializer Control Register 3* SRCTL4	- Serializer Control Register 4* SRCTL5	- Serializer Control Register 5* SRCTL6	- Serializer Control Register 6* SRCTL7	- Serializer Control Register 7* SRCTL8	- Serializer Control Register 8 (1)* SRCTL9	- Serializer Control Register 9 (1)* SRCTL10	- Serializer Control Register 10 (1)* SRCTL11	- Serializer Control Register 11 (1)* SRCTL12	- Serializer Control Register 12 (1)* SRCTL13	- Serializer Control Register 13 (1)* SRCTL14	- Serializer Control Register 14 (1)* SRCTL15	- Serializer Control Register 15 (1)* XTDM		- Transmit TDM Register* RTDM		- Receive TDM Register          * GBLCTL	- Global Control Register            * XGBLCTL	- Global Control Register            * RGBLCTL	- Global Control Register            * AMUTE	- Mute Control Register        * XINTCTL   - Transmitter Interrupt Control Register* RINTCTL   - Receiver Interrupt Control Register* RSTAT	- Receiver Status Register * XSTAT	- Transmitter Status Register * RSLOTCNT	- Receiver TDM Slot Counter* XSLOTCNT	- Transmitter TDM Slot Counter* XCLKCHK	- Transmit Clock Check Control Register* RCLKCHK	- Receive Clock Check Control Register* XBUF0	- Transmit Buffer for Serializer 0* XBUF1	- Transmit Buffer for Serializer 1* XBUF2	- Transmit Buffer for Serializer 2* XBUF3	- Transmit Buffer for Serializer 3* XBUF4	- Transmit Buffer for Serializer 4* XBUF5	- Transmit Buffer for Serializer 5* XBUF6	- Transmit Buffer for Serializer 6* XBUF7	- Transmit Buffer for Serializer 7* XBUF8	- Transmit Buffer for Serializer 8 (1)* XBUF9	- Transmit Buffer for Serializer 9 (1)* XBUF10	- Transmit Buffer for Serializer 10 (1)* XBUF11	- Transmit Buffer for Serializer 11 (1)* XBUF12	- Transmit Buffer for Serializer 12 (1)* XBUF13	- Transmit Buffer for Serializer 13 (1)* XBUF14	- Transmit Buffer for Serializer 14 (1)* XBUF15	- Transmit Buffer for Serializer 15 (1)* RBUF0	- Receive Buffer for Serializer 0* RBUF1	- Receive Buffer for Serializer 1* RBUF2	- Receive Buffer for Serializer 2* RBUF3	- Receive Buffer for Serializer 3* RBUF4	- Receive Buffer for Serializer 4* RBUF5	- Receive Buffer for Serializer 5* RBUF6	- Receive Buffer for Serializer 6* RBUF7	- Receive Buffer for Serializer 7* RBUF8	- Receive Buffer for Serializer 8 * RBUF9	- Receive Buffer for Serializer 9 * RBUF10	- Receive Buffer for Serializer 10* RBUF11	- Receive Buffer for Serializer 11 * RBUF12	- Receive Buffer for Serializer 12 * RBUF13	- Receive Buffer for Serializer 13 * RBUF14	- Receive Buffer for Serializer 14 * RBUF15	- Receive Buffer for Serializer 15 * DITCSRA0n	- Left (even TDM Slot) Channel Status Register File* DITCSRA1n* DITCSRA2n* DITCSRA3n* DITCSRA4n* DITCSRA5n* DITCSRB0n	- Right (even TDM Slot) Channel Status Register File* DITCSRB1n* DITCSRB2n* DITCSRB3n* DITCSRB4n* DITCSRB5n* DITUDRA0n	- Left (even TDM Slot) User Data Register File* DITUDRA1n* DITUDRA2n* DITUDRA3n* DITUDRA4n* DITUDRA5n* DITUDRB0n	- Right (even TDM Slot) User Data Register File* DITUDRB1n* DITUDRB2n* DITUDRB3n* DITUDRB4n* DITUDRB5n* *\******************************************************************************//******************************************************************************\* Step 2. Private Macros and Include files\******************************************************************************/#ifndef _CSL_MCASPHAL_H_#define _CSL_MCASPHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (MCASP_SUPPORT)/******************************************************************************\* Step 3. MISC section * Example:* #define _MCASP_BASE_GLOBAL   0xXXXXXXXXu\******************************************************************************/#if (CHIP_6713 | CHIP_DA610 | CHIP_6413 | CHIP_6418 | CHIP_6410) #define _MCASP_PORT_CNT        2#endif#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640) #define _MCASP_PORT_CNT        1#endif#if (CHIP_DM641 | CHIP_DM640)    #define _MCASP_CHANNEL_CNT    4#endif#if (CHIP_6413 | CHIP_6418 | CHIP_6410)    #define _MCASP_CHANNEL_CNT    6#endif#if (CHIP_DM642 | CHIP_6713)    #define _MCASP_CHANNEL_CNT    8#endif#if (CHIP_DA610)    #define _MCASP_CHANNEL_CNT    16#endif#define _MCASP_BASE_PORT0      0x01B4C000u#define _MCASP_BASE_PORT1      0x01B50000u/******************************************************************************\* Step 4. Module level register/field access macros\******************************************************************************/  /* -------------------------- */  /* Step 4.1 FIELD MAKE MACROS */  /* -------------------------- */  #define MCASP_FMK(REG,FIELD,x)\    _PER_FMK(MCASP,##REG,##FIELD,x)  #define MCASP_FMKS(REG,FIELD,SYM)\    _PER_FMKS(MCASP,##REG,##FIELD,##SYM)    /* ----------------------------------------- */  /* Step 4.2 RAW REGISTER/FIELD ACCESS MACROS */  /* ----------------------------------------- */  #define MCASP_ADDR(REG)\    _MCASP_##REG##_ADDR  #define MCASP_RGET(REG)\    _PER_RGET(_MCASP_##REG##_ADDR,MCASP,##REG)  #define MCASP_RSET(REG,x)\    _PER_RSET(_MCASP_##REG##_ADDR,MCASP,##REG,x)  #define MCASP_FGET(REG,FIELD)\    _MCASP_##REG##_FGET(##FIELD)  #define MCASP_FSET(REG,FIELD,x)\    _MCASP_##REG##_FSET(##FIELD,x)  #define MCASP_FSETS(REG,FIELD,SYM)\    _MCASP_##REG##_FSETS(##FIELD,##SYM)    /* --------------------------------------------------- */  /* Step 4.3 ADDRESS BASED REGISTER/FIELD ACCESS MACROS */  /* --------------------------------------------------- */  #define MCASP_RGETA(addr,REG)\    _PER_RGET(addr,MCASP,##REG)  #define MCASP_RSETA(addr,REG,x)\    _PER_RSET(addr,MCASP,##REG,x)  #define MCASP_FGETA(addr,REG,FIELD)\    _PER_FGET(addr,MCASP,##REG,##FIELD)  #define MCASP_FSETA(addr,REG,FIELD,x)\    _PER_FSET(addr,MCASP,##REG,##FIELD,x)  #define MCASP_FSETSA(addr,REG,FIELD,SYM)\    _PER_FSETS(addr,MCASP,##REG,##FIELD,##SYM)  /* -------------------------------------------------- */  /* Step 4.4 HANDLE BASED REGISTER/FIELD ACCESS MACROS */  /* -------------------------------------------------- */    /* For non-handle based Module : remove the following macros  (remove me)*/  /* See CDK Chapter 3. Module specification and CSL definitions ( remove me)*/      #define MCASP_ADDRH(h,REG)\    (Uint32)(&((h)->baseAddr[_MCASP_##REG##_OFFSET]))  #define MCASP_RGETH(h,REG)\    MCASP_RGETA(MCASP_ADDRH(h,##REG),##REG)  #define MCASP_RSETH(h,REG,x)\    MCASP_RSETA(MCASP_ADDRH(h,##REG),##REG,x)  #define MCASP_FGETH(h,REG,FIELD)\    MCASP_FGETA(MCASP_ADDRH(h,##REG),##REG,##FIELD)  #define MCASP_FSETH(h,REG,FIELD,x)\    MCASP_FSETA(MCASP_ADDRH(h,##REG),##REG,##FIELD,x)  #define MCASP_FSETSH(h,REG,FIELD,SYM)\    MCASP_FSETSA(MCASP_ADDRH(h,##REG),##REG,##FIELD,##SYM)/******************************************************************************\*  * _____________________* |                   |* |     P  I  D       |* |___________________|** PID  -  Peripheral Identification Register** FIELDS (msb -> lsb)* (r)  TYPE* (r)  CLASS* (r)  REV*\******************************************************************************/  #define _MCASP_PID_OFFSET		0  #define _MCASP_PID0_ADDR		(_MCASP_BASE_PORT0 + 4*_MCASP_PID_OFFSET)#if (_MCASP_PORT_CNT > 1)  #define _MCASP_PID1_ADDR		(_MCASP_BASE_PORT1 + 4*_MCASP_PID_OFFSET)#endif  #define _MCASP_PID_TYPE_MASK		0x00FF0000u  #define _MCASP_PID_TYPE_SHIFT		0x00000010u  #define  MCASP_PID_TYPE_DEFAULT	0x00000010u  #define  MCASP_PID_TYPE_OF(x)		_VALUEOF(x)  #define  MCASP_PID_TYPE_MCASP		0x00000010u   #define _MCASP_PID_CLASS_MASK		0x0000FF00u  #define _MCASP_PID_CLASS_SHIFT	0x00000008u  #define  MCASP_PID_CLASS_DEFAULT	0x00000001u  #define  MCASP_PID_CLASS_OF(x)	_VALUEOF(x)  #define  MCASP_PID_CLASS_SERPORT	0x00000001u    #define _MCASP_PID_REV_MASK		0x000000FFu  #define _MCASP_PID_REV_SHIFT		0x00000000u  #define  MCASP_PID_REV_DEFAULT	0x00000001u  #define  MCASP_PID_REV_OF(x)		_VALUEOF(x)  #define  MCASP_PID_REV_ONE		0x00000001u  #define  MCASP_PID_OF(x)		_VALUEOF(x)  #define MCASP_PID_DEFAULT (Uint32)( \     _PER_FDEFAULT(MCASP,PID,TYPE)\	| _PER_FDEFAULT(MCASP,PID,CLASS)\	| _PER_FDEFAULT(MCASP,PID,REV)\  )       #define MCASP_PID_RMK(type, class, rev) (Uint32)( \     _PER_FMK(MCASP,PID,TYPE,type)\	| _PER_FMK(MCASP,PID,CLASS,class)\	| _PER_FMK(MCASP,PID,REV,rev)\  )    #define _MCASP_PID_FGET(N,FIELD)\    _PER_FGET(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD)  #define _MCASP_PID_FSET(N,FIELD,field)\    _PER_FSET(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD,field)  #define _MCASP_PID_FSETS(N,FIELD,SYM)\  	_PER_FSETS(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD,##SYM)  #define _MCASP_PID0_FGET(FIELD) _MCASP_PID_FGET(0,##FIELD)#if (_MCASP_PORT_CNT > 1)  #define _MCASP_PID1_FGET(FIELD) _MCASP_PID_FGET(1,##FIELD)#endif   #define _MCASP_PID0_FSET(FIELD,f) _MCASP_PID_FSET(0,##FIELD,f)#if (_MCASP_PORT_CNT > 1)  #define _MCASP_PID1_FSET(FIELD,f) _MCASP_PID_FSET(1,##FIELD,f)#endif  #define _MCASP_PID0_FSETS(FIELD,SYM) _MCASP_PID_FSETS(0,##FIELD,##SYM)#if (_MCASP_PORT_CNT > 1)  #define _MCASP_PID1_FSETS(FIELD,SYM) _MCASP_PID_FSETS(1,##FIELD,##SYM)#endif/******************************************************************************\* Step 4.5