//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

ms2_serial.cpp

Abstract:  
        MainstoneII BSP Serial Driver.

Notes: 


--*/
#include <windows.h>
#include <types.h>
#include <ceddk.h>

#include <ddkreg.h>
#include <serhw.h>
#include <hw16550.h>
#include <Serdbg.h>

#include <bulverde.h>
#include <xllp_gpio.h>
#include <BUL16550.h>

#include <mainstoneii.h>
#include <xllp_bcr.h>

//---------------------------------Individual UART PORT -----------------------------------
//---------------------------------FUART PORT -----------------------------------
class CBulPdd16550FUART : public CBulPdd16550 
{
public:
    CBulPdd16550FUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj) {  };
	
    virtual BOOL Init() 
    {
        if (CBulPdd16550::Init() ) 
	{
            ConfigurePinout();
            //Enable FFUART clock
            m_pDCCLKReg->cken |= XLLP_CLKEN_FFUART ;
            return TRUE;
        }
        else
            return FALSE;
    }
	
    virtual void    SerialRegisterRestore() 
    {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
    }
	
private:
    BOOL ConfigurePinout()
    {
        //Initialize GPIO pins 
        //Write 0 on GPIO pins 39, 40 and 41 before configuring them as outputs.
        m_pGPIOReg->GPCR1 = ( XLLP_GPIO_BIT_FFDTR | XLLP_GPIO_BIT_FFTXD | XLLP_GPIO_BIT_FFRTS );
        
        //Configure direction of GPIO pins 34, 35, 36, 37 and 38 as input 
        //and GPIO pins 39, 40 and 41 as output
        m_pGPIOReg->GPDR1 &= ~( XLLP_GPIO_BIT_FFRXD | XLLP_GPIO_BIT_FFCTS | 
                                XLLP_GPIO_BIT_FFDCD | XLLP_GPIO_BIT_FFDSR | 
                                XLLP_GPIO_BIT_FFRI );
        m_pGPIOReg->GPDR1 |= (  XLLP_GPIO_BIT_FFTXD |  XLLP_GPIO_BIT_FFDTR |  XLLP_GPIO_BIT_FFRTS );
        
        //Configure GPIO pins 34, 35, 36, 37 and 38 for Alt_fn1. And pins 39, 40 and 41 for Alt_fn2.
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_FFRXD | XLLP_GPIO_AF_BIT_FFCTS | 
                                XLLP_GPIO_AF_BIT_FFDCD | XLLP_GPIO_AF_BIT_FFDSR | 
                                XLLP_GPIO_AF_BIT_FFRI  | XLLP_GPIO_AF_BIT_FFTXD | 
                                XLLP_GPIO_AF_BIT_FFDTR | XLLP_GPIO_AF_BIT_FFRTS );

        return TRUE;
    }
};

//---------------------------------BUART PORT -----------------------------------
class CBulPdd16550BUART : public CBulPdd16550 
{
public:
    CBulPdd16550BUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj) 
    { 
        m_pBCRReg = NULL;     
    };
	
    ~CBulPdd16550BUART() 
    {
        if (m_pBCRReg)
            MmUnmapIoSpace(m_pBCRReg,0);
    }
    
    virtual BOOL Init() 
    {
        if (m_pBCRReg==NULL) 
	{
            PHYSICAL_ADDRESS ioPhysicalBase = { MAINSTONEII_BASE_REG_PA_FPGA, 0 };
            m_pBCRReg =(PMAINSTONEII_BLR_REGS) MmMapIoSpace(ioPhysicalBase, sizeof(MAINSTONEII_BLR_REGS),FALSE) ;
        }
            
        if (m_pBCRReg!=NULL && CBulPdd16550::Init()) 
	{
            ConfigurePinout();
            //Enable BTUART clock
            m_pDCCLKReg->cken |= XLLP_CLKEN_BTUART ;
            return TRUE;
        }
        else
            return FALSE;
    }
	
    virtual void    SerialRegisterRestore() 
    {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
    }
	
    virtual void    SetDTR(BOOL bSet) 
    {
        if (bSet)
            m_pBCRReg->misc_wr &= ~XLLP_BCR_MISCWR1_BTDTR; 
        else
            m_pBCRReg->misc_wr |= XLLP_BCR_MISCWR1_BTDTR;             
    }
	
private:
    BOOL ConfigurePinout() 
    {
        //Configuring GPIO pins for BTUART
        //Initialize GPIO pins 
        //Write 0 on GPIO pins 43 and 45 before configuring them as outputs.
        m_pGPIOReg->GPCR1 = (XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);

        //Configure direction of GPIO pins 42 and 44 as input 
        //and GPIO pins 43 and 45 as output
        m_pGPIOReg->GPDR1 &= ~( XLLP_GPIO_BIT_BTRXD | XLLP_GPIO_BIT_BTCTS); 
        m_pGPIOReg->GPDR1 |=  ( XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);


        //Configure GPIO pins 42 and 44 for Alt_fn1. And pins 43 and 45 for Alt_fn2.
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_BTRXD | XLLP_GPIO_AF_BIT_BTCTS |
                                XLLP_GPIO_AF_BIT_BTTXD | XLLP_GPIO_AF_BIT_BTRTS );


        //Turn on the BTUART transceiver
        m_pBCRReg->misc_wr |= XLLP_BCR_MISCWR1_nBT_OFF; 

        return TRUE;
    }
	
    volatile PMAINSTONEII_BLR_REGS m_pBCRReg;
};

//---------------------------------SUART PORT -----------------------------------
class CBulPdd16550SUART : public CBulPdd16550 
{
public:
    CBulPdd16550SUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj)
    { 
        m_pBCRReg = NULL;     
    };
	
    ~CBulPdd16550SUART()
    {
        if (m_pBCRReg)
            MmUnmapIoSpace(m_pBCRReg,0);
    }
	
    virtual BOOL Init() 
    {

        if (m_pBCRReg==NULL) 
	{
            PHYSICAL_ADDRESS ioPhysicalBase = { MAINSTONEII_BASE_REG_PA_FPGA, 0 };
            m_pBCRReg =(PMAINSTONEII_BLR_REGS) MmMapIoSpace(ioPhysicalBase, sizeof(MAINSTONEII_BLR_REGS),FALSE);
        }
		
        if (m_pBCRReg!=NULL  && CBulPdd16550::Init())
	{
            ConfigurePinout();
            m_pDCCLKReg->cken |= XLLP_CLKEN_STUART ;
            return TRUE;
        }
		
        else
            return FALSE;
    }
	
    virtual void    SerialRegisterRestore() 
    {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
        
    }

private:
    BOOL ConfigurePinout() 
    {
        //Initialize GPIO pins 
        //Write 0 on GPIO pin 47 before configuring it as output.
        //Verify whether to write zero or not?
        //pHWHead->pGPIOReg->GPCR_y |=  (GPIO_47);
        m_pGPIOReg->GPSR1 =  (XLLP_GPIO_BIT_STD_TXD);

        //Configure direction of GPIO pin 46 as input and GPIO pin 47 as output
        m_pGPIOReg->GPDR1 &= (~XLLP_GPIO_BIT_STD_RXD);
        m_pGPIOReg->GPDR1 |= ( XLLP_GPIO_BIT_STD_TXD);

        //Configure GPIO pin 46 for Alt_fn2. And, GPIO pin 47 for Alt_fn1.
        m_pGPIOReg->GAFR1_L &= ~(XLLP_GPIO_AF_BIT_STD_RXD_MASK | XLLP_GPIO_AF_BIT_STD_TXD_MASK);
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_STD_RXD | XLLP_GPIO_AF_BIT_STD_TXD);

        //Configure IrDA transceiver for SIR mode and full distance power.  
        //pHWHead->pBCRReg->misc_wr &= ~(IRDA_MD_MASK | IRDA_FIR_MASK);
        m_pBCRReg->misc_wr &= (~XLLP_BCR_MISCWR1_IRDA_MD & ~XLLP_BCR_MISCWR1_IRDA_FIR);

        return TRUE;
    }

    volatile PMAINSTONEII_BLR_REGS m_pBCRReg;
};

CSerialPDD * CreateSerialObject(LPTSTR lpActivePath, PVOID pMdd,PHWOBJ pHwObj, DWORD DeviceArrayIndex)
{
    CSerialPDD * pSerialPDD = NULL;
    switch (DeviceArrayIndex ) 
    {
        case 0:default:
            pSerialPDD = new CPdd16550(lpActivePath,pMdd, pHwObj);
            break;
        case 0x80:
            pSerialPDD = new CBulPdd16550FUART (lpActivePath,pMdd, pHwObj);
            break;
        case 0x81:
            pSerialPDD = new CBulPdd16550BUART(lpActivePath,pMdd, pHwObj);
            break;
        case 0x82:
            pSerialPDD = new CBulPdd16550SUART(lpActivePath,pMdd, pHwObj);
            break;
    }
	
    if (pSerialPDD && pSerialPDD->Init()!= TRUE) 
    {
        delete pSerialPDD;
        pSerialPDD = NULL;
    }
	
    return pSerialPDD;
}

void DeleteSerialObject(CSerialPDD * pSerialPDD)
{
    if (pSerialPDD)
    delete pSerialPDD;
}