library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity stepermotor is
	port(
		clk50M	:in std_logic;
		a,na,b,nb :out std_logic
		);
end stepermotor;

architecture be of stepermotor is
	signal clk800k	:std_logic;
	signal cnt 	:integer range 0 to 62499;
	signal state :integer range 0 to 7;

begin

 process--(clk50M)
 begin
	wait until rising_edge(clk50M);
	if(cnt=62499)then
		cnt<=0;
		clk800k<=not clk800k;
	else
		cnt<=cnt+1;
	end if;
end process;

  process
  begin
	wait until rising_edge(clk800k);
	if(state=7)then
		state<=0;
	else
		state<=state+1;
	end if;
	
	case state is
	 when 0 =>
		a<='0';
		na<='1';
		b<='1';
		nb<='1';
	 when 1 =>
		a<='0';
		na<='1';
		b<='0';
		nb<='1';
	 when 2 =>
		a<='1';
		na<='1';
		b<='0';
		nb<='1';
	 when 3 =>
		a<='1';
		na<='0';
		b<='0';
		nb<='1';
	when 4 =>
		a<='1';
		na<='0';
		b<='1';
		nb<='1';
	when 5 =>
		a<='1';
		na<='0';
		b<='1';
		nb<='0';
	when 6 =>
		a<='1';
		na<='1';
		b<='1';
		nb<='0';
	when 7 =>
		a<='0';
		na<='1';
		b<='1';
		nb<='0';
	end case;
 end process;

end be;