?? hc08ap64.h
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/***********************************************************************
*
* 文 件: HC08AP64.h
* 功 能: HC08AP64寄存器定義頭文件.
*
***********************************************************************/
struct bool{
unsigned BIT0:1; /* LSB First */
unsigned BIT1:1;
unsigned BIT2:1;
unsigned BIT3:1;
unsigned BIT4:1;
unsigned BIT5:1;
unsigned BIT6:1;
unsigned BIT7:1;
};
volatile unsigned char PTA @0x00; /* port A */
volatile unsigned char PTB @0x01; /* port B */
volatile unsigned char PTC @0x02; /* port C */
volatile unsigned char PTD @0x03; /* port D */
volatile unsigned char DDRA @0x04; /* data direction port A */
volatile unsigned char DDRB @0x05; /* data direction port B */
volatile unsigned char DDRC @0x06; /* data direction port C */
volatile unsigned char DDRD @0x07; /* data direction port D */
// TIMER section
volatile unsigned char LEDA @0x0c; /* Port-A LED Control Register */
volatile unsigned char SPCR @0x10; /* SPI Control Register */
volatile unsigned char SPSCR @0x11; /* SPI Status and Control Register */
volatile unsigned char SPDR @0x12; /* SPI Data Register */
volatile unsigned char SCC1 @0x13; /* SCI Control Register1 */
volatile unsigned char SCC2 @0x14; /* SCI Control Register2 */
volatile unsigned char SCC3 @0x15; /* SCI Control Register3 */
volatile unsigned char SCS1 @0x16; /* SCI Status Register1 */
volatile unsigned char SCS2 @0x17; /* SCI Status Register2 */
volatile unsigned char SCDR @0x18; /* SCI Data Register */
volatile unsigned char SCBR @0x19; /* SCI Baud Rate Register */
volatile unsigned char KBSCR @0x1A; /* Keyboard Staturs and Contrl Register */
volatile unsigned char KBIER @0x1B; /* Keyboard Keyboard Interrupt and Enable Register */
volatile unsigned char INTSCR2 @0x1C;/* IRQ2 Status and Control Register */
volatile unsigned char CONF2 @0x1d; /* Configuration Register 2 */
volatile unsigned char INTSCR1 @0x1e;/* IRQ Status and Control Register 1*/
volatile unsigned char CONF1 @0x1f; /* Configuration Register 1 */
volatile unsigned char T1SC @0x20; /* Timer 1 Status and Control Register */
volatile unsigned int T1CNT @0x21; /* timer 1 Counter Register */
volatile unsigned char T1CNTH @0x21; /* Timer 1 Counter High */
volatile unsigned char T1CNTL @0x22; /* Timer 1 Counter Low */
volatile unsigned int T1MOD @0x23; /* timer 1 modulo */
volatile unsigned char T1MODH @0x23; /* timer 1 modulo high */
volatile unsigned char T1MODL @0x24; /* timer 1 modulo low */
volatile unsigned char T1SC0 @0x25; /* timer 1 chan 0 status/ctrl */
volatile unsigned char T1CH0H @0x26; /* timer 1 chan 0 high */
volatile unsigned char T1CH0L @0x27; /* timer 1 chan 0 low */
volatile unsigned char T1SC1 @0x28; /* timer 1 chan 1 status/ctrl */
volatile unsigned int T1CH1H @0x29; /* timer 1 chan 1 high */
volatile unsigned char T1CH1L @0x2A; /* timer 1 chan 1 low */
volatile unsigned char T2SC @0x2B; /* Timer 2 Status and Control Register */
volatile unsigned char T2CNTH @0x2C; /* Timer 2 Counter High */
volatile unsigned char T2CNTL @0x2D; /* Timer 2 Counter Low */
volatile unsigned int T2MOD @0x2E; /* timer 2 modulo */
volatile unsigned char T2MODH @0x2E; /* timer 2 modulo high */
volatile unsigned char T2MODL @0x2F; /* timer 2 modulo low */
volatile unsigned char T2SC0 @0x30; /* timer 2 chan 0 status/ctrl */
volatile unsigned char T2CH0H @0x31; /* timer 2 chan 0 high */
volatile unsigned char T2CH0L @0x32; /* timer 2 chan 0 low */
volatile unsigned char T2SC1 @0x33; /* timer 2 chan 1 status/ctrl */
volatile unsigned char T2CH1H @0x34; /* timer 2 chan 1 high */
volatile unsigned char T2CH1L @0x35; /* timer 2 chan 1 low */
volatile unsigned char PCTL @0x36; /* PLL Control Register */
volatile unsigned char PBWC @0x37; /* PLL Bandwidth Control Register */
volatile unsigned int PMS @0x38; /* PLL Multiplier Select Register */
volatile unsigned char PMSH @0x38; /* PLL Multiplier Select Register High */
volatile unsigned char PMSL @0x39; /* PLL Multiplier Select Register Low */
volatile unsigned char PMRS @0x3A; /* PLL VCO Range Select Register */
volatile unsigned char PMDS @0x3B; /* PLL Reference Divider Select Register */
// 紅外線串口 03-7-18 9:22
volatile unsigned char IRSCC1 @0x40; /* IRSCI Control Register 1 */
volatile unsigned char IRSCC2 @0x41; /* IRSCI Control Register 2 */
volatile unsigned char IRSCC3 @0x42; /* IRSCI Control Register 3 */
volatile unsigned char IRSCS1 @0x43; /* IRSCI Status Register 1*/
volatile unsigned char IRSCS2 @0x44; /* IRSCI Status Register 2*/
volatile unsigned char IRSCDR @0x45; /* IRSCI Data Register */
volatile unsigned char IRSCBR @0x46; /* IRSCI Baud Rate Register */
volatile unsigned char IRSCIRCR @0x47;/* IRSCI Infrared Control Register */
// I2C BUS
volatile unsigned char MMADR @0x48; /* MMIIC Address Register */
volatile unsigned char MMCR1 @0x49; /* MMIIC Control Register 1 */
volatile unsigned char MMCR2 @0x4a; /* MMIIC Control Register 2 */
volatile unsigned char MMSR @0x4b; /* MMIIC Status Register */
volatile unsigned char MMDTR @0x4c; /* MMIIC Data Transmit Register*/
volatile unsigned char MMDRR @0x4d; /* MMIIC Data Receive Register*/
volatile unsigned char MMCRDR @0x4e; /* MMIIC CRC Data Register*/
volatile unsigned char MMFDR @0x4f; /* MMIIC Frequency Divider Register*/
volatile unsigned char TBCR @0x51; /* Timebase Control Register*/
// ADC 轉換
volatile unsigned char ADSCR @0x57; /* ADC Status and Control Register */
volatile unsigned char ADICLK @0x58; /* ADC Clock Control Register */
volatile unsigned char ADRH0 @0x59; /* ADC Data Register High 0 */
volatile unsigned char ADRL0 @0x5A; /* ADC Data Register Low 0 */
volatile unsigned char ADRL1 @0x5B; /* ADC Data Register Low 1 */
volatile unsigned char ADRL2 @0x5C; /* ADC Data Register Low 2 */
volatile unsigned char ADRL3 @0x5D; /* ADC Data Register Low 3 */
volatile unsigned char ADASCR @0x5e; /* ADC Auto-scan Control Register*/
// SIM section
volatile unsigned char SBSR @0xfe00; /* SIM break status register */
volatile unsigned char SRSR @0xfe01; /* SIM reset status register */
volatile unsigned char SBFCR @0xfe03; /* SIM break control register */
volatile unsigned char INT1 @0xfe04; /* BREAK address register */
volatile unsigned char INT2 @0xfe05; /* BREAK address register low */
volatile unsigned char INT3 @0xfe06; /* BREAK address register low */
volatile unsigned char FLCR @0xfe08; /* FLASH Control Register */
volatile unsigned char FLBPR @0xfe09; /* FLASH Block Protect */
volatile unsigned int BRK @0xfe0c; /* BREAK address register high */
volatile unsigned char BRKH @0xfe0c; /* BREAK address register high */
volatile unsigned char BRKL @0xfe0d; /* BREAK address register high */
volatile unsigned char BRKSCR @0xfe0e; /* BREAK status/ctrl register */
volatile unsigned char LVISR @0xfe0f; /* LVI status register */
volatile unsigned char COPCR @0xffff; /* COP control register */
//bool varible define
/* Timer Bit */
#define TOF1 ((struct bool*)&T1SC)->BIT7 //Timer overflow flag
#define TOIE1 ((struct bool*)&T1SC)->BIT6 //
#define TSTOP1 ((struct bool*)&T1SC)->BIT5 //
#define TRST1 ((struct bool*)&T1SC)->BIT4 //
#define PS2_1 ((struct bool*)&T1SC)->BIT2 //
#define PS1_1 ((struct bool*)&T1SC)->BIT1 //
#define PS0_1 ((struct bool*)&T1SC)->BIT0 //
/* Timer Bit */
#define TOF2 ((struct bool*)&T2SC)->BIT7 //Timer overflow flag
#define TOIE2 ((struct bool*)&T2SC)->BIT6 //
#define TSTOP2 ((struct bool*)&T2SC)->BIT5 //
#define TRST2 ((struct bool*)&T2SC)->BIT4 //
#define PS2_2 ((struct bool*)&T2SC)->BIT2 //
#define PS1_2 ((struct bool*)&T2SC)->BIT1 //
#define PS0_2 ((struct bool*)&T2SC)->BIT0 //
/* Timer Channel 0 */
#define CH0F ((struct bool*)&T1SC0)->BIT7 //Timer overflow flag
#define CH0IE ((struct bool*)&T1SC0)->BIT6 //
#define MS0B ((struct bool*)&T1SC0)->BIT5 //
#define MS0A ((struct bool*)&T1SC0)->BIT4 //
#define ELS0B ((struct bool*)&T1SC0)->BIT3
#define ELS0A ((struct bool*)&T1SC0)->BIT2 //
#define TOV0 ((struct bool*)&T1SC0)->BIT1 //
#define CH0MAX ((struct bool*)&T1SC0)->BIT0 //
/* Timer Channel 1 */
#define CH1F ((struct bool*)&T1SC1)->BIT7 //Timer overflow flag
#define CH1IE ((struct bool*)&T1SC1)->BIT6 //
#define MS1A ((struct bool*)&T1SC1)->BIT4 //
#define ELS1B ((struct bool*)&T1SC1)->BIT3
#define ELS1A ((struct bool*)&T1SC1)->BIT2 //
#define TOV1 ((struct bool*)&T1SC1)->BIT1 //
#define CH1MAX ((struct bool*)&T1SC1)->BIT0 //
#define PGM ((struct bool*)&FLCR)->BIT0 //
#define ERASE ((struct bool*)&FLCR)->BIT1 //
#define MASS ((struct bool*)&FLCR)->BIT2 //
#define HVEN ((struct bool*)&FLCR)->BIT3 //
#define INT_ACK1 ((struct bool*)&INTSCR1)->BIT2 // 中斷 清除 //
#define INT_ACK2 ((struct bool*)&INTSCR2)->BIT2 // 中斷 清除 //
// 串行通訊狀態寄存器位變量
#define ENSCI ((struct bool*)&SCC1)->BIT6
#define SCTIE ((struct bool*)&SCC2)->BIT7
#define TCIE ((struct bool*)&SCC2)->BIT6
#define SCRIE ((struct bool*)&SCC2)->BIT5
#define ILIE ((struct bool*)&SCC2)->BIT4
#define TE ((struct bool*)&SCC2)->BIT3
#define RE ((struct bool*)&SCC2)->BIT3
#define TE ((struct bool*)&SCC2)->BIT3
#define SCTE ((struct bool*)&SCS1)->BIT7 // 發送緩沖區空標志
#define TC ((struct bool*)&SCS1)->BIT6 // 發送完成標志
#define SCRF ((struct bool*)&SCS1)->BIT5 // 接收緩沖區滿標志
// PLL控制寄存器
#define PLLIE ((struct bool*)&PCTL)->BIT7 // PLL中斷允許位
#define PLLF ((struct bool*)&PCTL)->BIT6 // PLL中斷標志位
#define PLLON ((struct bool*)&PCTL)->BIT5 // PLL開關
#define BCS ((struct bool*)&PCTL)->BIT4 // 系統時鐘源選擇
// PLL帶寬控制寄存器
#define AUTO ((struct bool*)&PBWC)->BIT7 // PLL自動帶寬控制位
#define LOCK ((struct bool*)&PBWC)->BIT6 // PLL鎖相指示位
#define ACQ ((struct bool*)&PBWC)->BIT5 // PLL獲取模式狀態位
// TBCR tbm控制寄存器
#define TBIF ((struct bool*)&TBCR)->BIT7
#define TBR2 ((struct bool*)&TBCR)->BIT6
#define TBR1 ((struct bool*)&TBCR)->BIT5
#define TBR0 ((struct bool*)&TBCR)->BIT4
#define TACK ((struct bool*)&TBCR)->BIT3
#define TBIE ((struct bool*)&TBCR)->BIT2
#define TBON ((struct bool*)&TBCR)->BIT1
// SSBFCR 定義
#define BCFE ((struct bool*)&SBFCR)->BIT7
// KBI模塊寄存器定義
#define KEYF ((struct bool*)&KBSCR)->BIT3
#define ACKK ((struct bool*)&KBSCR)->BIT2
#define IMASKK ((struct bool*)&KBSCR)->BIT1
#define MODEK ((struct bool*)&KBSCR)->BIT0
// ADSCR控制寄存器定義
#define COCO ((struct bool*)&ADSCR)->BIT7
#define AIEN ((struct bool*)&ADSCR)->BIT6
#define ADCO ((struct bool*)&ADSCR)->BIT5
// 口線定義
#define PTA7 ((struct bool*)&PTA)->BIT7
#define PTA6 ((struct bool*)&PTA)->BIT6
#define PTA5 ((struct bool*)&PTA)->BIT5
#define PTA4 ((struct bool*)&PTA)->BIT4
#define PTA3 ((struct bool*)&PTA)->BIT3
#define PTA2 ((struct bool*)&PTA)->BIT2
#define PTA1 ((struct bool*)&PTA)->BIT1
#define PTA0 ((struct bool*)&PTA)->BIT0
#define PTB7 ((struct bool*)&PTB)->BIT7
#define PTB6 ((struct bool*)&PTB)->BIT6
#define PTB5 ((struct bool*)&PTB)->BIT5
#define PTB4 ((struct bool*)&PTB)->BIT4
#define PTB3 ((struct bool*)&PTB)->BIT3
#define PTB2 ((struct bool*)&PTB)->BIT2
#define PTB1 ((struct bool*)&PTB)->BIT1
#define PTB0 ((struct bool*)&PTB)->BIT0
#define PTC7 ((struct bool*)&PTC)->BIT7
#define PTC6 ((struct bool*)&PTC)->BIT6
#define PTC5 ((struct bool*)&PTC)->BIT5
#define PTC4 ((struct bool*)&PTC)->BIT4
#define PTC3 ((struct bool*)&PTC)->BIT3
#define PTC2 ((struct bool*)&PTC)->BIT2
#define PTC1 ((struct bool*)&PTC)->BIT1
#define PTC0 ((struct bool*)&PTC)->BIT0
#define PTD7 ((struct bool*)&PTD)->BIT7
#define PTD6 ((struct bool*)&PTD)->BIT6
#define PTD5 ((struct bool*)&PTD)->BIT5
#define PTD4 ((struct bool*)&PTD)->BIT4
#define PTD3 ((struct bool*)&PTD)->BIT3
#define PTD2 ((struct bool*)&PTD)->BIT2
#define PTD1 ((struct bool*)&PTD)->BIT1
#define PTD0 ((struct bool*)&PTD)->BIT0
// IRQ1,2004-9-27 11:17
#define IRQ1F ((struct bool*)&INTSCR1)->BIT3
#define ACK1 ((struct bool*)&INTSCR1)->BIT2
#define IMASK1 ((struct bool*)&INTSCR1)->BIT1
#define MODE1 ((struct bool*)&INTSCR1)->BIT0
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