#ifndef __PLX_IOCTL_H#define __PLX_IOCTL_H/******************************************************************************* * Copyright (c) 2003 PLX Technology, Inc. * * PLX Technology Inc. licenses this software under specific terms and * conditions.  Use of any of the software or derviatives thereof in any * product without a PLX Technology chip is strictly prohibited. * * PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY, * EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  PLX makes no guarantee * or representations regarding the use of, or the results of the use of, * the software and documentation in terms of correctness, accuracy, * reliability, currentness, or otherwise; and you rely on the software, * documentation and results solely at your own risk. * * IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES * OF ANY KIND.  IN NO EVENT SHALL PLX'S TOTAL LIABILITY EXCEED THE SUM * PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER. * ******************************************************************************//****************************************************************************** * * File Name: * *      PlxIoctl.h * * Description: * *      This file contains the common I/O Control messages shared between *      the driver and the PCI API. * * Revision History: * *      05-31-03 : PCI SDK v4.10 * ******************************************************************************///#include <linux/fcntl.h>#include <linux/unistd.h>#include <linux/ioctl.h>#include <PlxTypes.h>#include <PciTypes.h>#define PLX_IOCTL_CODE_BASE 	0x0#define PLX_IOCTL_NEW		0x80#define PLX_IOCTL_FPGA_TMAC_PHY   0xc0#define PLX_MAGIC                'P'#define IOCTL_MSG( code, type )        _IOWR(         \                                         PLX_MAGIC, \                                         code,      \                                         type  \                                         )                                         #define IOCTL_NEW( code )        _IO(    PLX_MAGIC, \	                                 code )/************************************** *  IO-CTL-CODE for telecom card  **************************************/typedef enum _DRIVER_MSGS{            MSG_APP_MANAGE_CMD = PLX_IOCTL_CODE_BASE,		    MSG_PCI_REGISTER_CMD,     MSG_RULE_CMD,             /*for fpga module command code*/	    MSG_FPGA_MOD_CMD = PLX_IOCTL_FPGA_TMAC_PHY,        /*For MAC Modeule Command Code*/    MSG_MAC_MOD_CMD,            /*For PHY Module Command Code*/    MSG_PHY_MOD_CMD,    MSG_READ_DMA_BUFFER_CMD,        MSG_PKT_SEND_CMD,    MSG_STATISTICS_CMD,    MSG_VERSION_CMD,    MSG_FLOW_CTRL_CMD,    MSG_MISC_CMD} DRIVER_MSGS;/************************************** *  IO SUB-CMD-CODE   **************************************/typedef enum _APP_MANAGE_CMD{        APP_ID_ALLOCATE = 0,		    APP_ID_FREE,    APP_MEM_ALLOCATE ,    APP_MEM_FREE,    APP_MEM_MAP_TELL,    APP_MEM_MAP_CALL,    APP_RECV_WAITISR_SET,    APP_STAT_REGTODRV_SET,    APP_STAT_UNREGTODRV_SET,    APP_STAT_PHYADDRESS_GET,    APP_STAT_STARTTIMER_SET,    APP_STAT_STOPTIMER_SET,    APP_STAT_BASEPORT_SET,    APP_STAT_WAITISR_SET	} APP_MANAGE_CMD;typedef enum _PCI_REGISTER_CMD{        PCI_REGISTER_READ = 0,     PCI_REGISTER_WRITE} PCI_REGISTER_CMD;typedef enum _RULE_CMD{        RULE_ADD = 0,    RULE_DEL ,    RULE_MODIFY,    RULE_READ,    DEFAULT_RULE_ADD,    DEFAULT_RULE_DEL,    DEFAULT_RULE_MODIFY,    DEFAULT_RULE_READ } RULE_CMD;typedef enum _FLOW_CTRL_CMD{    FLOW_CTRL_PKT_FWRD = 0,    FLOW_CTRL_PKT_DROP,    FLOW_CTRL_FLOW_FWRD,    FLOW_CTRL_FLOW_DROP}FLOW_CTRL_CMD;typedef enum _MISC_CMD{    VLAN_HDR_RESRV = 0,    VLAN_HDR_DROP,    PPPOE_HDR_RESRV,    PPPOE_HDR_DROP,    EMPTY_PKT_RULE,    ERROR_PKT_RULE,    SET_SLICE_LEN,    HEART_ACTIVE,    ENV_CONFIG}MISC_CMD;typedef struct _PCI_MEMORY{    unsigned long UserAddr;    unsigned long PhysicalAddr;    unsigned long Size;} PCI_MEMORY;typedef struct _DEVICE_LOCATION{	unsigned char    BusNumber;	unsigned char    SlotNumber;	unsigned short   DeviceId;	unsigned short   VendorId;	unsigned char    SerialNumber[12];}DEVICE_LOCATION;typedef struct _TELL_ARRAY_INFO{	unsigned long	block;	unsigned long	id;} ARRAY_INFO;typedef struct _RuleAction{    unsigned char store_flag:1;    unsigned char sample_flag:1;    unsigned char forward_flag:1;    unsigned char statistics_flag:1;    unsigned char slice_flag:1;    unsigned char drop_flag:1;    unsigned char valid:1;    unsigned char RSV:1;		}RULE_ACTION;typedef struct rule_struct {    unsigned long index;    unsigned long app_id;		        unsigned long dip;    unsigned long dip_mask;    unsigned long sip;    unsigned long sip_mask;    unsigned short dp;    unsigned short sp;    unsigned char pt;    unsigned char region;    RULE_ACTION act;    unsigned char ucPri;}RULE_STRUCT;typedef struct _ALLRVERDION{    unsigned long              ulCliVer;      //major[8]:middle[16]:minor[8]    unsigned long              ulDriverVer;   //major[8]:middle[16]:minor[8]    unsigned long              ulFpgaVer;     //major[8]:middle[16]:minor[8]}ALLRVERDION;/*RULE Structure*/typedef struct _MSGS_RULEACC{    unsigned int uiCmd;	       /*sub-cmd-code From FPGA_CMD*/    unsigned int uiRetVal; 	    union{        RULE_STRUCT   stRule;    }u;     }MSGS_RULEACC;//  Used to pass all arguments down to the drivertypedef struct _IOCTLDATA{    unsigned int uiCmd;    int iRet;     unsigned int offset;    unsigned int value;    union    {         unsigned long data[2];        DEVICE_LOCATION Device;        PCI_MEMORY  PciMemory;        ARRAY_INFO   ArrayInfo;         ALLRVERDION Version;    } u;} IOCTLDATA;#define PLX_IOCTL_APP_MANAGE_MSG           IOCTL_MSG(MSG_APP_MANAGE_CMD, IOCTLDATA)#define PLX_IOCTL_PCI_REGISTER_MSG         IOCTL_MSG(MSG_PCI_REGISTER_CMD, IOCTLDATA)#define PLX_IOCTL_RULE_MSG                 IOCTL_MSG(MSG_RULE_CMD, MSGS_RULEACC)/*For FPGA Modeule Command Code*///#define PLX_IOCTL_FPGA_MSG                 IOCTL_MSG(MSG_FPGA_MOD_CMD, MSGS_FPGAACC)/*For MAC Modeule Command Code*///#define PLX_IOCTL_MAC_MSG                  IOCTL_MSG( MSG_MAC_MOD_CMD, MSGS_MACACC)/*IoCtl Code For Phy Module Only*///#define PLX_IOCTL_PHY_MSG                  IOCTL_MSG( MSG_PHY_MOD_CMD, MSGS_PHYACC)#define PLX_IOCTL_DMA_BUFFER_MSG           IOCTL_MSG(MSG_READ_DMA_BUFFER_CMD, IOCTLDATA)//#define PLX_IOCTL_PKT_SEND_MSG             IOCTL_MSG(MSG_PKT_SEND_CMD, )#define PLX_IOCTL_STATISTICS_MSG           IOCTL_MSG(MSG_STATISTICS_CMD, IOCTLDATA)#define PLX_IOCTL_VERSION_MSG     IOCTL_MSG(MSG_VERSION_CMD, IOCTLDATA)#define PLX_IOCTL_FLOW_CTRL_MSG  IOCTL_MSG(MSG_FLOW_CTRL_CMD, IOCTLDATA)#define PLX_IOCTL_MISC_MSG    IOCTL_MSG(MSG_MISC_CMD, IOCTLDATA)#endif