//DSP driver debugging
#include <std.h>
#include <stdio.h>
#include "TCI648x_Global.h"
#include "TCI648x_Gpio.h"
#include "TCI648x_DDR2Ctl.h"
#include "TCI648x_Timer.h"
#include "TCI648x_Emif.h"
#include "TCI648x_Edma3.h"
#include "TCI648x_Boot.h"

//control debug
#define PASSED_DEBUG

#pragma DATA_ALIGN(srcBuf, 1024)
unsigned int srcBuf[1024];
unsigned int dstBuf[1024];
main()
{
	int i;
	int j;
	unsigned short DataSink[2048];
	unsigned int * pU32DDR2;

	EDMA3_PaRAM PaRAMSet64;
	unsigned char *pSrcBuf = (unsigned char *)srcBuf;
	unsigned char *pDstBuf = (unsigned char *)dstBuf;

	unsigned int Emif_Ce_Mode[4] = {ACCESS_TYPE_SYNC,ACCESS_TYPE_SYNC,ACCESS_TYPE_SYNC,ACCESS_TYPE_SYNC};
	unsigned int *pEmif;
	unsigned short *pEmifCe3; 

	//1.PLL debug
	DR_PLLCtl_Init();
	//peripherals configuration
	//enable Timer0, Timer1, GPIO, EMAC/MDIO, EMIFA and DDR2
	DR_PeripheralCfg();


#ifndef PASSED_DEBUG 
	//1.1 flash debug connected to FPGA
	pEmifCe3 = (unsigned short *)0xB0000000;
	DR_Emif_Init(Emif_Ce_Mode);
	
	// write the data into CE3, namely Flash, the memory space is 64Mbit -- start from 0xB0000000
	for(j=0; j<2048; j++)
	{
		DataSink[j] = (j<<8) + (j & 0xFF);
	}

	//the sector burning
	ROM_Sector_Burn(DataSink,2048,EPROM_BASEADDR);

#endif

	
#ifndef PASSED_DEBUG 
	//2.EMIF debug
	pEmif = (unsigned int *)0xC0000000;
	DR_Emif_Init(Emif_Ce_Mode);
	// write the data into CE2, the memory space is 64KB -- start from 0xA0000000
	for(i=0; i<1024; i++)
	{
		//pEmif[i] = (i<<16) + i ;
		pEmif[i] = i;
	}

	//validate the data reading from CE2
	for(i=0; i<1024; i++)
	{
		//if(pEmif[i] != (((i<<16) + i) & 0x03FF03FF))
		if(i != pEmif[i])
		{
			printf("Error Encountered when debugging for EMIFA!\n");
			exit(0);
		}
	}
#endif

#ifndef PASSED_DEBUG
#endif

	//3.DDR2 controller debug
	printf("DDR2 test begin\n");

	pU32DDR2 = (unsigned int *)0xE0000000;
	DR_DDR2Ctl_Init();

	//debug of operation of read/write for DDR2 SDRAM -- 256MB from 0xE0000000 to 0xEFFFFFFF
	for(i=0; i<65535*8; i++)
	{
		pU32DDR2[i] = 0;  //(i<<16) + i;
	}
    printf("DDR2 write 0 finished\n");

	for(i=0; i<65535*8; i++)
	{
		pU32DDR2[i] = 0xffffffff;  //(i<<16) + i;
/*
        if(pU32DDR2[i] != 0xffffffff) //((i<<16) + i))
	  	{
			printf("Error ,i=%d\n",i);
            pU32DDR2[i] = 0xffffffff;
		}
		*/	
   	}

	printf("DDR2 write f finished\n");
		
	for(i=0; i<65535*8; i++)
	{
		if(pU32DDR2[i] != 0xffffffff) //((i<<16) + i))
		{
			printf("Error ,i=%d\n",i);
		//	exit(0);
		}
	}

		


//#ifndef PASSED_DEBUG
	//4.GPIO debug
	//GPIO0,1,2 are used to control the LEDS
	DR_Gpio_Init();

	while(1)
	{
		DR_Gpio_Set(GPIO0,1);
		DR_Gpio_Set(GPIO1,1);
		DR_Gpio_Set(GPIO2,1);
		for(i=0; i<1000*10000; i++)
		{
		}
		
		DR_Gpio_Set(GPIO0,0);
		DR_Gpio_Set(GPIO1,0);
		DR_Gpio_Set(GPIO2,0);
		for(i=0; i<1000*10000; i++)
		{
		}
	}

	//5.EDMA3 debug
	DR_Edma3_Init();
	//PaRAM configuration
	PaRAMSet64.m_wOpt.b1_SAM = 0;
	PaRAMSet64.m_wOpt.b1_DAM = 0;
	PaRAMSet64.m_wOpt.b1_SYNCDIM = 1;	//AB-synchronized
	PaRAMSet64.m_wOpt.b1_STATIC = 1;	//set is static
	PaRAMSet64.m_wOpt.b3_FWID = 0;
	PaRAMSet64.m_wOpt.b1_TCCMOD = 0;	//normal completion
	PaRAMSet64.m_wOpt.b6_TCC = TCC36;
	PaRAMSet64.m_wOpt.b1_TCINTEN = 1;	//Transfer complete interrupt is enable
	PaRAMSet64.m_wOpt.b1_ITCINTEN = 0;
	PaRAMSet64.m_wOpt.b1_TCCHEN = 0;
	PaRAMSet64.m_wOpt.b1_ITCCHEN = 0;
	PaRAMSet64.m_wOpt.b4_PRIVID = 0;
	PaRAMSet64.m_wOpt.b1_PRIV = 0;		//user level privilege
	PaRAMSet64.m_wSRC = (unsigned int)0xE0000000;
	PaRAMSet64.m_hwBCNT = 0x01;		 	//2048 array	
	PaRAMSet64.m_hwACNT = 2048;			//2 bytes
	PaRAMSet64.m_wDST = (unsigned int)pSrcBuf;
	PaRAMSet64.m_hwDSTBIDX = 0x00;
	PaRAMSet64.m_hwSRCBIDX = 0x00;
	PaRAMSet64.m_hwBCNTRLD = 0;
	PaRAMSet64.m_hwLINK = 0xFFFF;		//Null link
	PaRAMSet64.m_hwDSTCIDX = 0;
	PaRAMSet64.m_hwSRCCIDX = 0;
	PaRAMSet64.m_hwCCNT = 0x01;

	DR_QdmaTransferStart((EDMA3_PaRAM *)&PaRAMSet64, 0);

	DR_DmaTransferFinish(TCC36);

	//6.Timer debug
	DR_Timer_Init(MODE_64BIT_GP,SELECT_TIMER0);
	//start the timer0
	DR_TimerStart(SELECT_TIMER0,ENAMODE_ONETIME);		//1 for one time mode; 2 for continous mode
	//delay 10s for test
	DR_TimeDelay(10000, TIMEUNIT_MS, SELECT_TIMER0);

//#endif

}