?? at91sam7x256.inc
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;- ----------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;- ----------------------------------------------------------------------------
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;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;- ----------------------------------------------------------------------------
;- File Name : AT91SAM7X256.h
;- Object : AT91SAM7X256 definitions
;- Generated : AT91 SW Application Group 01/16/2006 (16:36:22)
;-
;- CVS Reference : /AT91SAM7X256.pl/1.15/Wed Nov 2 13:56:49 2005//
;- CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
;- CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
;- CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
;- CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
;- CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
;- CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
;- CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
;- CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
;- CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
;- CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
;- CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
;- CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
;- CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
;- CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
;- CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
;- CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
;- CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
;- CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
;- CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
;- CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
;- CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
;- CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
;- ----------------------------------------------------------------------------
;- Hardware register definition
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR System Peripherals
;- *****************************************************************************
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
;- *****************************************************************************
^ 0 ;- AT91S_AIC
AIC_SMR # 128 ;- Source Mode Register
AIC_SVR # 128 ;- Source Vector Register
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 8 ;- Reserved
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command Register
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- End of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
AIC_DCR # 4 ;- Debug Control Register (Protect)
# 4 ;- Reserved
AIC_FFER # 4 ;- Fast Forcing Enable Register
AIC_FFDR # 4 ;- Fast Forcing Disable Register
AIC_FFSR # 4 ;- Fast Forcing Status Register
;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0:SHL:5) ;- (AIC) External Sources Code Label Low-level Sensitive
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) External Sources Code Label Negative Edge triggered
AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode
AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Peripheral DMA Controller
;- *****************************************************************************
^ 0 ;- AT91S_PDC
PDC_RPR # 4 ;- Receive Pointer Register
PDC_RCR # 4 ;- Receive Counter Register
PDC_TPR # 4 ;- Transmit Pointer Register
PDC_TCR # 4 ;- Transmit Counter Register
PDC_RNPR # 4 ;- Receive Next Pointer Register
PDC_RNCR # 4 ;- Receive Next Counter Register
PDC_TNPR # 4 ;- Transmit Next Pointer Register
PDC_TNCR # 4 ;- Transmit Next Counter Register
PDC_PTCR # 4 ;- PDC Transfer Control Register
PDC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Debug Unit
;- *****************************************************************************
^ 0 ;- AT91S_DBGU
DBGU_CR # 4 ;- Control Register
DBGU_MR # 4 ;- Mode Register
DBGU_IER # 4 ;- Interrupt Enable Register
DBGU_IDR # 4 ;- Interrupt Disable Register
DBGU_IMR # 4 ;- Interrupt Mask Register
DBGU_CSR # 4 ;- Channel Status Register
DBGU_RHR # 4 ;- Receiver Holding Register
DBGU_THR # 4 ;- Transmitter Holding Register
DBGU_BRGR # 4 ;- Baud Rate Generator Register
# 28 ;- Reserved
DBGU_CIDR # 4 ;- Chip ID Register
DBGU_EXID # 4 ;- Chip ID Extension Register
DBGU_FNTR # 4 ;- Force NTRST Register
# 180 ;- Reserved
DBGU_RPR # 4 ;- Receive Pointer Register
DBGU_RCR # 4 ;- Receive Counter Register
DBGU_TPR # 4 ;- Transmit Pointer Register
DBGU_TCR # 4 ;- Transmit Counter Register
DBGU_RNPR # 4 ;- Receive Next Pointer Register
DBGU_RNCR # 4 ;- Receive Next Counter Register
DBGU_TNPR # 4 ;- Transmit Next Pointer Register
DBGU_TNCR # 4 ;- Transmit Next Counter Register
DBGU_PTCR # 4 ;- PDC Transfer Control Register
DBGU_PTSR # 4 ;- PDC Transfer Status Register
;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (DBGU) Reset Status Bits
;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;- *****************************************************************************
^ 0 ;- AT91S_PIO
PIO_PER # 4 ;- PIO Enable Register
PIO_PDR # 4 ;- PIO Disable Register
PIO_PSR # 4 ;- PIO Status Register
# 4 ;- Reserved
PIO_OER # 4 ;- Output Enable Register
PIO_ODR # 4 ;- Output Disable Registerr
PIO_OSR # 4 ;- Output Status Register
# 4 ;- Reserved
PIO_IFER # 4 ;- Input Filter Enable Register
PIO_IFDR # 4 ;- Input Filter Disable Register
PIO_IFSR # 4 ;- Input Filter Status Register
# 4 ;- Reserved
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