`timescale 1ns/10ps
module	IEZW_TOP(clk,reset,Pass,IEZW_in,In_IEZW,threshold,In_flag,Out_flag,Out_Data,wire_wren,wire_wraddress,wire_MemoryInData);
input		clk,reset;
input	[2:0]	Pass;
input	[7:0]	threshold;
input	[8:0]	IEZW_in;
input	[1:0]	In_IEZW;

output		In_flag,Out_flag;
output	[8:0]	Out_Data;
output		wire_wren;
output	[18:0]	wire_wraddress;
output	[8:0]	wire_MemoryInData;

wire		In_flag,Out_flag,wire_datapath_flag;
wire	[2:0]	wire_Pass;
wire	[2:0]	wire_Done;
wire	[7:0]	wire_threshold;
wire	[4:0]	wire_DataPath;
wire		wire_wren,wire_wren_ll3,wire_wren_datapath,wire_wren_out;
wire	[8:0]	wire_IEZW_out,wire_WrDat_datapath;
wire	[8:0]	Out_Data,wire_MemoryInData,wire_MemoryOutData;
wire	[18:0]	wire_ll3_wraddress,wire_datapath_wraddress,wire_out_rdaddress,wire_datapath_rdaddress;
wire	[18:0]	wire_rdaddress,wire_wraddress;


IEZW_Control		control(.clk(clk),.reset(reset),.Pass(wire_Pass),.Done(wire_Done),.Out_EZW_DataPath(wire_DataPath));


threshold_reg		reg_0(.clk(clk),.reset(reset),.division(wire_DataPath[1]),.read(wire_DataPath[4]),.In_threshold(threshold),.Out_threshold(wire_threshold));
Pass_reg		pass_0(.clk(clk),.reset(reset),.read(wire_DataPath[4]),.In_Pass(Pass),.Out_Pass(wire_Pass));

most_low_freq		mlf(.clk(clk),.reset(reset),.ready(wire_DataPath[3]),.IEZW_in(IEZW_in),.write_en(wire_wren_ll3),.IEZW_out(wire_IEZW_out),.address_W(wire_ll3_wraddress),.Done(wire_Done[1]));

IEZW_DataPath		DataPath(.clk(clk),.reset(reset),.ready(wire_DataPath[2]),.In_IEZW(In_IEZW),.threshold(wire_threshold),
		.Read_Data(wire_MemoryOutData),.In_flag(wire_datapath_flag),.Write_en(wire_wren_datapath),.Write_Data(wire_WrDat_datapath),.Read_address(wire_datapath_rdaddress),.Write_address(wire_datapath_wraddress),.Done(wire_Done[0]));

RAM256 		RAM(.clock(clk),.wren(wire_wren),.data(wire_MemoryInData),.wraddress(wire_wraddress),.rdaddress(wire_rdaddress),.q(wire_MemoryOutData));

IEZW_output		out_0(.clk(clk),.reset(reset),.ready(wire_DataPath[0]),.In_Data(wire_MemoryOutData),.write_en(wire_wren_out),.flag(Out_flag),.Out_Data(Out_Data),.address_R(wire_out_rdaddress),.Done(wire_Done[2]));

assign	wire_wren=(wire_DataPath[0])?wire_wren_out:((wire_DataPath[3])?wire_wren_ll3:wire_wren_datapath);
assign	wire_MemoryInData=(wire_DataPath[3])?wire_IEZW_out:wire_WrDat_datapath;
assign	wire_wraddress=(wire_DataPath[3])?wire_ll3_wraddress:wire_datapath_wraddress;
assign	In_flag=(wire_DataPath[3])?wire_wren_ll3:wire_datapath_flag;
assign	wire_rdaddress=(wire_DataPath[0])?wire_out_rdaddress:wire_datapath_rdaddress;

endmodule


module Pass_reg(clk,reset,read,In_Pass,Out_Pass);
input		clk,reset,read;
input	[2:0]	In_Pass;

output	[2:0]	Out_Pass;

reg	[2:0]	Out_Pass;

always @(posedge clk) begin
	if(!reset)
		Out_Pass=0;
	else
		if(read)
			Out_Pass=In_Pass;
		else
			Out_Pass=Out_Pass;
end
endmodule


module threshold_reg(clk,reset,division,read,In_threshold,Out_threshold);
input		clk,reset,division,read;
input	[7:0]	In_threshold;

output	[7:0]	Out_threshold;

reg	[7:0]	Out_threshold;

always @(posedge clk) begin
	if(!reset)
		Out_threshold=0;
	else
		if(read)
			Out_threshold=In_threshold;
		else
			if(division)
				Out_threshold=Out_threshold >> 1;
			else
				Out_threshold=Out_threshold;
end
endmodule


module IEZW_Control(clk,reset,Pass,Done,Out_EZW_DataPath);
input		clk,reset;
input	[2:0]	Pass;
input	[2:0]	Done;

output	[4:0]	Out_EZW_DataPath;

parameter	S0=0;
parameter	S1=1;
parameter	S2=2;
parameter	S3=3;
parameter	S4=4;
parameter S5=5;
parameter S6=6;


reg	[2:0]	NextState,CurrentState;
reg	[2:0]	Pass_counter;
reg	[4:0]	Out_EZW_DataPath;

always@(posedge clk or negedge reset)
begin
	if(!reset)
		CurrentState = S0;
	else
		CurrentState = NextState;
end

always@(CurrentState or reset or Pass or Pass_counter or Done)
begin
	case(CurrentState)
		S0:begin
			if(!reset)
				NextState = S0;
			else
				NextState = S1;
		end
		
		S1:begin
		//	if(read_threshold)
				NextState = S2;//S2
		//	else
		//		NextState = S1;
		end

		S2:begin
			if(Done[1])
				NextState = S3;
			else
				NextState = S2;
		end 

		S3:begin
			if(Done[0])
				NextState = S4;
			else
				NextState = S3;
		end
		
		S4:begin
			if(Pass_counter==Pass)
				NextState = S5;
			else
				NextState = S3;
		end
				
		S5:begin
			if(Done[2])
				NextState = S6;
			else
				NextState = S5;
		end
		
		S6:	NextState = S6;
			
			
		default:NextState = S0;
	endcase
end

always@(CurrentState)
begin
	case(CurrentState)
		S0:	Out_EZW_DataPath=5'b0_0_0_0_0;//reset system
		S1:	Out_EZW_DataPath=5'b1_0_0_0_0;//read threshold
		S2:	Out_EZW_DataPath=5'b0_1_0_0_0;//read LL3 subband
		S3:	Out_EZW_DataPath=5'b0_0_1_0_0;//start IEZW
		S4:	Out_EZW_DataPath=5'b0_0_0_1_0;//shift threshold
		S5:	Out_EZW_DataPath=5'b0_0_0_0_1;//output Data
		S5:	Out_EZW_DataPath=5'b0_0_0_0_0;//output Data
		default:Out_EZW_DataPath=5'b0_0_0_0_0;
	endcase
end

always@(posedge clk)
begin
	if(!reset)
		Pass_counter=0;
	else
		if(Done[0])
			Pass_counter=Pass_counter+1'b1;
		else
			Pass_counter=Pass_counter;
end

endmodule



module most_low_freq(clk,reset,ready,IEZW_in,write_en,IEZW_out,address_W,Done);

parameter size=512;

input		clk,reset,ready;
input	[8:0]	IEZW_in;
output		write_en;
output	[8:0]	IEZW_out;
output	[18:0]	address_W;
output		Done;

reg		Done,write_en;
reg	[18:0]	address_W;

reg	[8:0]	IEZW_out;

always @(negedge clk)
begin
	if(!reset || !ready) begin
		address_W=(size/8*size/8);
	end
	else
		if(address_W==(size/8*size/8))
			address_W=19'h00000;
		else
			address_W=address_W+1'b1;
end

always@(negedge clk)
begin
	if(!reset || !ready)
		Done=1'b0;
	else
		if(address_W==(size/8*size/8))
			Done=1'b1;
		else
			Done=1'b0;
end

always@(negedge clk)
begin
	if(!reset || !ready) begin
		write_en=1'b0;
	end
	else begin
		if(address_W==19'h00000)
			write_en=1'b1;
		else if(address_W==(size/8*size/8))
			write_en=1'b0;
		else
			write_en=write_en;
	end
end

always@(negedge clk)
begin
	if(!reset || !ready) begin
		IEZW_out=9'h000;
	end
	else begin
		IEZW_out=IEZW_in;
	end
end
endmodule


module IEZW_output(clk,reset,ready,In_Data,write_en,flag,Out_Data,address_R,Done);

parameter size=512;

input		clk,reset,ready;
input	[8:0]	In_Data;
output		write_en;
output		flag;
output	[8:0]	Out_Data;
output	[18:0]	address_R;
output		Done;

reg		Done,write_en,flag;
reg	[18:0]	address_R;

reg	[8:0]	Out_Data;

always @(negedge clk)
begin
	if(!reset || !ready) begin
		address_R=(size*size);
	end
	else
		if(address_R==(size*size))
			address_R=19'h0000;
		else
			address_R=address_R+1'b1;
end

always@(negedge clk)
begin
	if(!reset || !ready) begin
		flag=1'b0;
		write_en=1'b0;
	end
	else begin
		if(address_R==19'h00000)begin
			flag=write_en;
			write_en=1'b1;
		end
		else if(address_R==(size*size))begin
			flag=write_en;
			write_en=1'b0;
		end
		else begin
			flag=write_en;
			write_en=write_en;
		end
	end
end



always@(flag or In_Data)
begin
	if(!reset || !ready)
		Out_Data=9'h000;
	else
		Out_Data=In_Data;
end

always@(negedge clk)
begin
	if(!reset || !ready)
		Done=1'b0;
	else
		if(address_R==(size*size))
			Done=1'b1;
		else
			Done=1'b0;
end

endmodule


module IEZW_DataPath(clk,reset,ready,In_IEZW,threshold,Read_Data,In_flag,Write_en,Write_Data,Read_address,Write_address,Done);
input		clk,reset,ready;
input	[1:0]	In_IEZW;
input	[7:0]	threshold;
input	[8:0]	Read_Data;

output		In_flag;
output		Write_en;
output	[8:0]	Write_Data;
output	[18:0]	Read_address,Write_address;
output		Done;

wire		wire_flag_21,wire_counter_two,wire_flag;
wire	[4:0]	wire_counter,wire_counter_stack,wire_counter_21;
wire	[18:0]	wire_address_counter;

wire		Write_en,wire_en_smap,wire_en_saq;
wire	[8:0]	Write_Data,wire_smap_data,wire_saq_data;
wire	[18:0]	Read_address,Write_address,smap_address,saq_address;
wire		Done;

IEZW_counter			counter(.clk(clk),.reset(reset),.ready(ready),.In_IEZW(In_IEZW),.wire_en_smap(wire_en_smap),.flag_21(wire_flag_21),.counter_two(wire_counter_two),.flag(wire_flag),.counter(wire_counter),.counter_stack(wire_counter_stack),.counter_21(wire_counter_21),.address_counter(wire_address_counter),.Done(Done));
IEZW_SMAP_process			SMAP(.clk(clk),.reset(reset),.ready(ready),.flag(wire_flag),.In_IEZW(In_IEZW),.threshold(threshold),.counter(wire_counter),.counter_stack(wire_counter_stack),.address_counter(wire_address_counter),.Write_en(wire_en_smap),.Write_Data(wire_smap_data),.Write_address(smap_address));
IEZW_SAQ_process			SAQ(.clk(clk),.reset(reset),.ready(ready),.flag(wire_flag),.counter_two(wire_counter_two),.threshold(threshold),.In_IEZW(In_IEZW),.Read_Data(Read_Data),.counter_21(wire_counter_21),.address_counter(wire_address_counter),.flag_21(wire_flag_21),.Write_en(wire_en_saq),.Write_Data(wire_saq_data),.address(saq_address));

assign	Write_en=wire_en_saq | wire_en_smap;
assign	Write_Data=(~wire_flag | wire_en_smap)?wire_smap_data:wire_saq_data;
assign	Write_address=(~wire_flag | wire_en_smap)?smap_address:saq_address;
assign	Read_address=(wire_counter_two)?saq_address:19'h00000;
assign	In_flag=wire_en_saq | !wire_flag;
endmodule



module IEZW_counter(clk,reset,ready,In_IEZW,wire_en_smap,flag_21,counter_two,flag,counter,counter_stack,counter_21,address_counter,Done);

parameter	size=512;

input		clk,reset,ready;
input		wire_en_smap;
input	[1:0]	In_IEZW;
input		flag_21;

output		counter_two,flag;
output	[4:0]	counter,counter_stack,counter_21;
output	[18:0]	address_counter;
output		Done;	

reg		counter_two,flag,frey_reg;
reg	[4:0]	counter,counter_stack,counter_21;
reg	[18:0]	address_counter;
reg		Done_reg,Done;
reg		stack_reset,stack_flag,SMAP_flag,SAQ_flag;

always@(negedge clk)
begin
	if(!reset || !ready) begin
		counter=0;
		counter_two=1'b0;
	end
	else
		if(flag==1'b0) begin
			if(counter>=counter_stack) begin
				counter=0;
			end
			else begin
				counter=counter+1'b1;
			end
			counter_two=1'b1;
		end
		else begin
			if(counter_two)
				if(wire_en_smap)
					counter_two=1'b1;
				else
					counter_two=1'b0;
			else
				if(flag_21==1'b1)
					counter_two=counter_two;
				else
					counter_two=1'b1;