?? fencounter6.vhd
字號:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY fencounter6 IS
GENERIC(LEN: integer:=6);
PORT(clkin: in std_logic;
Rf: in std_logic;
Cout,fenset2,fenalarm2: out std_logic;
A: out std_logic_vector(3 downto 0));
END fencounter6;
ARCHITECTURE behave of fencounter6 IS
signal s_cnt:integer range 0 to LEN -1;
signal r_cnt:integer range 0 to LEN -1;
begin
process(clkin,Rf,s_cnt)
variable cnt:integer range 0 to LEN-1;
variable c:std_logic;
begin
if Rf='0' then
cnt:=0;
elsif rising_edge(clkin)then
if cnt = LEN -1 then
c:='1';
else
c:='0';
end if;
if cnt =LEN -1 then
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
if cnt = 0 then
fenset2 <='1';
fenalarm2 <='1';
elsif cnt = 3 then
fenset2 <='0';
fenalarm2 <='1';
else
fenset2 <='0';
fenalarm2 <='0';
end if;
s_cnt<=cnt;
A<=conv_std_logic_vector(s_cnt,4);
Cout<=c;
end process;
end behave;
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