LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY counter12 IS
	GENERIC(LEN: integer:=12);
	PORT(clkin: in std_logic;	
		 Rf: in std_logic;
		 Cout: out std_logic;
		 A: out std_logic_vector(3 downto 0));
END counter12;

ARCHITECTURE behave of counter12 IS
	signal s_cnt:integer range 0 to LEN -1;
	signal r_cnt:integer range 0 to LEN -1;
begin			
	process(clkin)
			variable cnt:integer range 0 to LEN-1;
			variable c:std_logic;
	begin
		if Rf='0' then
			cnt:=0;
			c:='0';
		elsif rising_edge(clkin)then
			if cnt = LEN -1 and c='0' then
				c:='1';
			elsif cnt = LEN -1 and c='1' then
				c:='0';
			end if;
			if cnt =LEN -1 then
				cnt:=0;
			else
				cnt:=cnt+1;
			end if;
		end if;
		s_cnt<=cnt;
		A<=conv_std_logic_vector(s_cnt,4);
		Cout<=c;
	end process;
end behave;