#include <stdio.h>#include "spi.h"#include "type.h"#include "flash_Drv.h"#include <cdefBF549.h>#include <stdio.h>#include <string.h>#include <sys\exception.h>

#include <cdefBF549.h>
#include <ccblkfn.h>
#include <sys/exception.h>
#include <signal.h>
#include <stdlib.h>

#define BUFFSIZE 1024#define FLASH_BUFF_SIZE 256#define CHKSUM_SIZE 8#define NULL ((void *)0)
//#define SPI0_SEL	0x0200
//#define SPI0_CLR    ~0x0200


#define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
/* PLL_DIV Macros														*/
#define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/

void Init_PLL(void);
//section("MEM_SDRAM0") unsigned char load_buffer[1000000];unsigned char buffer[512];


void SPIflash_SEL(void)
{
	  *pSPI0_FLG |= 0x0200;
}
void SPIflash_CLR(void)

{  
	  *pSPI0_FLG &= ~0x0200;
}
void delay(unsigned int temp){	unsigned int i;	for(i=0;i<temp;i++)		i=i;}void Init_DDR(void)
{
    // release the DDR controller from reset as per spec
    *pEBIU_RSTCTL |= 0x0001;
    ssync();

	*pEBIU_AMGCTL = 0x0009;
	*pEBIU_DDRCTL0 = 0x218A8411L;
	*pEBIU_DDRCTL1 = 0x100e2222L;
	*pEBIU_DDRCTL2 = 0x00000021L;	
    ssync();

}


void Init_EBIU(void)
{
	*pEBIU_AMBCTL0	= 0x7bb07bb0;
	*pEBIU_AMBCTL1	= 0xffc0ffc0;
	*pEBIU_AMGCTL	= 0x0002;
}


void Init_PLL(void)
{
	*pSIC_IWR0 |= 0x1;			// enable PLL wakeup
	*pPLL_CTL = SET_MSEL(15);	/* (27MHz Xtal x (MSEL=15))::CCLK=405MHz		*/

	idle();

	*pPLL_DIV = SET_SSEL(3);	/* (405MHz/(SSEL=3))::SCLK=135MHz				*/
	ssync();
	*pVR_CTL = 0x40FB;
	ssync();
	
	idle();
}

int main(){	int i,j;	unsigned int id;											   	unsigned char stat = 0;	Init_PLL();	Init_EBIU();	printf("SPI Init\n");	spi_init();	
	for(i=0;i<512;i++)
		buffer[i] = i;
		id = read_id();	chip_erase();
	id = read_id();
	printf("id is %x\n",id);
				load_flash(buffer, 512);		printf("END.\n");	while(1);}