?? svpwm1.asm
字號:
**************************************************
* Em&c of Zhejiang University *
* Svpwm for rectifier *
* File name: svpwm.asm *
* Author: K.Y.Huang *
* Programming on 2002.4.20 *
* Running in Tms320f240 which works at 20M *
**************************************************
.include "c240app.h"
.globl START
.sect ".vectors"
B START ;reset interrupt handler
INT1 B INT1
INT2 B PWMSER ;PWM interrupt handler
INT3 B INT3 ;ZBAO,ADC start interrupt handler
INT4 B INT4
INT5 B INT5
INT6 B INT6
; .space 16*6;
.sect "table"
sintab .include sin1.tab ; sine wave for 3-phase
; voltage input
**********************************************************
** This program is ready for a test system with a
** relatively low designed voltage.
** The pu system is applied to simplify the fix point
** calculation, 4.12 numeric format(4 interger&sign +
** 12 fractional) is used except otherwise specified.
** In 4.12 format, base values is 1000h(=1)
** voltage: Vbase=1000h(4.12)=100v
** current: Ibase=1000h(4.12)=5A
** rated phase voltage: Umax=100v=1000h(4.12)
** rated output DC voltage: VDC=250v=2800h(4.12)
** angle: [0:ffffh] = [0:360]
** Switch Frequency fpwm=10k, Tpwm=100us
**********************************************************
**********************************************************
* Varibles and constants defination and initialization
**********************************************************
.data
*** axis transformation constants
sqrt32 .set 0ddbh ;sqrt(3)/2, 4.12
sqrt3inv .set 093dh ;1/sqrt(3),4.12
*** pwm modulation constant
PWMPRD .set 1000 ;pwm period=2*1000
;Tswt=2000*50=100us,(Cpuclk=50ns)
Umax .set 1000h ;Umax=100v=1000h(4.12)
.bss acch,1 ;save acc low bit
.bss accl,1 ;save acc low bit
.bss index,1 ;sine wave look-up index[0-200]
.bss indexB,1 ;sine wave ub table
.bss tmp,1 ;temp variable
.bss tmp1,1 ;temp variable
.bss ua,1 ;phase voltage ua(4.12)
.bss ub,1 ;phase voltage ub(4.12)
.bss uc,1 ;phase voltage uc(4.12)
.bss usalfa,1 ;alfa-axis reference voltage
.bss usbeta,1 ;beta-axis reference voltage
.bss usd,1 ;d-axis voltage of grid,4.12
.bss usq,1 ;q-axis voltage of grid,4.12
.bss sintetaA,1 ;Q15
.bss sintetaB,1 ;Q15
.bss sintetaC,1 ;Q15
.bss ia,1 ;phase current ia (4.12)
.bss ib,1 ;phase current ib (4.12)
.bss ic,1 ;phase current ic (4.12)
.bss ialfa,1 ;alfa-axis current
.bss ibeta,1 ;beta-axis current
.bss id,1 ;d-axis current
.bss iq,1 ;q-axis current
.bss sinTeta_cm,1 ;alfa-beta to d-q sin value,Q15
.bss cosTeta_cm,1 ;alfa-beta to d-q cos value,Q15
.bss sinTmp,1 ;temp sinTeta_cm value,Q15
.bss cosTmp,1 ;temp cosTeta_cm value,Q15
.bss index_sin,1
.bss index_cos,1
.bss t1,1 ;SVPWM T1 (see SVPWM references for details)
.bss t2,1 ;SVPWM T2 (see SVPWM references for details)
.bss X,1 ;SVPWM variable
.bss Y,1 ;SVPWM variable
.bss Z,1 ;SVPWM variable
.bss theta,1
.bss sector,1
.bss Vref1,1 ;variable for sector calculation
.bss Vref2,1 ;variable for sector calculation
.bss Vref3,1 ;variable for sector calculation
.bss VDC,1 ;DC Bus Voltage
.bss VDCinvT,1 ;PWMPRD/VDC
.bss taon,1 ;PWM commutation instant phase 1
.bss tbon,1 ;PWM commutation instant phase 2
.bss tcon,1 ;PWM commutation instant phase 3
************************************************************
* End Varibles and constants defination and initialization
************************************************************
.text
START:
**********************************************************
* Board General Settings
clrc xf
clrc cnf ;B0 as data block
**********************************************************
**********************************************************
** Disable the watchdog timer
ldp #WDCR>>7
splk #06fh,WDCR
splk #055h,WDKEY
splk #0aah,WDKEY
splk #06fh,WDCR
**********************************************************
**********************************************************
** initialize the event manager
** GPTimer1 acting as Full PWM
** Enable timer1 == 0 interrupt on INT2
** All other pins are IO
ldp #224
; set SYSCLK and PLL for C240
splk #00000010b,CKCR0
;PLL disableed
;LPM0
;ACLK enabled
;SYSCLK 5
splk #10111011b,CKCR1
;for c240 CPUclk=20M,crystle=10M,so 10M clk for ACLK
;bit7-4=1011 10M clock for ACLK
;bit3=0,do not divide PLL
;bit2-0=001,PLL ratio x2
splk #11000011b,CKCR0
;bit7-6=10, Pll enabled
;bit1=1 ACLK enabled
;bit0=1 SYSCLK=CPUCLK/2
splk #40c0h,SYSCR ;set CLKOUT to be CPUCLK
;clear all reset variables
lacc SYSSR
and #69ffh
sacl SYSSR
;set zero wait states for extenal memory
* lacc #0004h
* sacl *
* out *,WSGR
;clear all EV registers
ldp #232
zac
sacl GPTCON
sacl T1CNT
sacl T1CMPR
sacl T1PR
sacl T1CON
sacl T2CNT
sacl T2CMPR
sacl T2PR
sacl T2CON
sacl T3CNT
sacl T3CMPR
sacl T3PR
sacl T3CON
sacl COMCON
sacl ACTR
sacl SACTR;
sacl DBTCON
sacl CMPR1
sacl CMPR2
sacl CMPR3
sacl SCMPR1
sacl SCMPR2
sacl SCMPR3
sacl CAPCON
sacl CAPFIFO
sacl CAP1FIFO
sacl CAP2FIFO
sacl CAP3FIFO
sacl CAP4FIFO
;initialise PWM, with 2us dead-band
splk #666h,ACTR
;bit15-12 not used,no space vector
;PWM6/PWM5 -active low/active high
;PWM4/PWM3 -active low/active high
;PWM2/PWM1 -active low/active high
splk #05f8h,DBTCON ;enable DB,Tdb=2us
;bit15-8=05h,bit4-3=11(x8)
;bit7-5=111,enable 3 dead-band timers
;bit2-0,reserved
splk #200, CMPR1
splk #300, CMPR2
splk #500, CMPR3
splk #0207h,COMCON ;first enable pwm operation
;bit14-13=00 reload full compare when T1CNT=0
;bit12=0 disable Space Vector
;bit11-10=00 reload full compare action when T1CNT=0
;bit9=1, enable full compare output
;bit8-3,disable simple compare units
;bit2-0=111,full compare units in pwm mode
splk #8207h,COMCON ;then enable compare operation
splk #PWMPRD,T1PR ;set T1 period
splk #0, T1CNT
splk #0a800h,T1CON
;bit15-14=10,ignore emulation suspend
;bit13-11=101,continous count up/down mode
;bit10-8=000,x/1 prescalar
;bit7=0,use own TENABLE
;bit6=0,disable timer, enable later
;bit5-4=00,internal clock
;bit3-2=00,reload compare register when T1CNT=0
;bit1=0, disable timer compare operation
;bit0=0, reserved in T1CON,enable timer 1
lacc T1CON
or #40h ;bit6=1
sacl T1CON ;enable timer1
;configure IO\function MUXing of pins
ldp #225
splk #000fh,OCRA ;ports A&B all IO except ADCs
splk #00f9h,OCRB ;ports Cas non IO except IOPC2&3
splk #0ff08h,PCDATDIR ;bit IOPC3
;initialse ar7 as the stack for context save space reserved
;DARAM B2 60h-7fh (page 0)
lar ar7,#79h
; A/D initialization
ldp #224
sacl ADCFIFO1
sacl ADCFIFO1
splk #0005h,ADCTRL2
;prescaler for a 15M oscillator
;bit2-0=101 means X16, so Tad=16*6/15=6.4us
** END EV initialization and PWM configuization
**********************************************************
**********************************************************
** Variables initialization
ldp #4 ;B0 data block locating page6-7
zac
sacl index
sacl Vref1
sacl Vref2
sacl Vref3
splk #2800h,VDC ;VDC=250v while Vbase=100v
;Vdc=2.5 in 4.12
splk #190h,VDCinvT ;PWMPRD/Vdc=400=190h
setc OVM
spm 0 ;no shift after multiplication
setc sxm ;sign extension mode
** End Variables initialization
*********************************************************
*********************************************************
** Enable Interrupts
;clear EV IFR and IMR register
ldp #EVIFRA>>7
splk #07ffh,EVIFRA
;bit15-11,reserved,no defination
;bit10, T1 overflow int flag,write into 1 to reset
;bit9, T1 underflow int flag
;bit8, T1 compare int flag
;bit7, T1 period int flag
;bit6-4, simple compare int flag
;bit3-1, full compare int flag
;bit0, power sourse protect int flag
splk #00ffh,EVIFRB
;bit15-8,reserved
;bit7, T3 overflow int flag,write into 1 to reset
;bit6, T3 underflow int flag
;bit5, T3 compare int flag
;bit4, T3 period int flag
;bit3, T2 overflow int flag
;bit2, T2 underflow int flag
;bit1, T2 compare int flag
;bit0, T2 period int flag
splk #000fh,EVIFRC
;bit15-4,reserved
;bit3, Capture4 int flag,write into 1 to reset
;bit2, Capture3 int flag,write into 1 to reset
;bit1, Capture2 int flag,write into 1 to reset
;bit0, Capture1 int flag,write into 1 to reset
splk #0200h,EVIMRA ;enable T1 underflow int
;bit15-11 reserved
;bit10-7, T1 overflow,underflow,
;compare and period int, 1 enabled
;bit6-4, simple compare int
;bit3-1, full compare3,2,1 int
;bit0, PDPINT
splk #0000h,EVIMRB ;bit7-0, T2 and T3 int
splk #0000h,EVIMRC ;bit3-0, capture4-1 int
;set IMF for int2 and clear any flags
;int2 (pwm interrupt) is used for motor control
;synchronization
ldp #0
lacc #0ffh
sacl IFR ;reset IFR, write into 1 to clear
;bit5-0,flags of int6-int1
lacc #000010b
sacl IMR ;enable int2
ldp #4
clrc INTM ;enable all ints,now may serve ints
; setc INTM
** End enable interrupts
** End initialization
*************************************************************
END:
;KICK_DOG
B END
; call PWMSER
PWMSER: ;PWM Underflow interrupt serve program
*************************************************************
** Synchronization of the control algrithm with the PWM *
** Underflow interrupt *
; context saving
larp ar7 ;making ar7 as current AR,ar7=79h
mar *- ;ar7=78h
sst #1,*- ;content of ST1 saved to 78h,then ar7=77h
sst #0,*- ;content of ST0 saved to 77h,then ar7=76h
sach *- ;Acc high saved to 76h,then ar7=75h
sacl *- ;Acc low saved to 75h,then ar7=74
; end context saving
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Following program is to test SVPWM agrithm. ;
;; The desired input three-phase sine-voltages ;
;; is get by lookup table. ;
;; Ua=Umax*sin(teta) ;
;; Ub=Umax*sin(teta-120) ;
;; Uc=Umax*sin(teta+120) ;
;; theta=omiga*t ;
ldp #4
mar *,ar5 ;making ar5 as current AR
lacl index ;; judging if index is in
and #0ffh ;; 0-200, if larger than
sub #201 ;; 200,then index=index-201
bcnd sin_cirA,LT
sacl index
sin_cirA:
; calculating ua
lacl index
add #sintab ;look up sine table
sacl tmp
lar ar5,tmp
lacl *
sacl sintetaA ;get value of sintetaA
lt sintetaA ; Q15
mpy #Umax ;ua=Umax*sin(teta),Umax(Q12)=1000h
pac ; ua(Q12), for Q15*Q12=Q27, get off
sach ua,1 ; low 16 bits,then Q11,so left-shift
; 1 bit, Q12
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -