/*****************************************************************************Copyright (c) 2004 Analog Devices.  All Rights Reserved.Developed by Analog Devices Australia - Unit 3, 97 Lewis Road,Wantirna, Victoria, Australia, 3152.  Email: ada.info@analog.comTHIS SOFTWARE IS PROPRIETARY & CONFIDENTIAL.  By using this module youagree to the terms of the associated Analog Devices License Agreement.******************************************************************************$Revision: 2438 $$Date: 2005-09-13 15:51:40 +1000 (Tue, 13 Sep 2005) $Project:        IEEE 802.16 LibraryTitle:          Rate 1/2 Tail Biting Convolutional EncoderAuthor(s):      Michael Lopez (michael.lopez@analog.com)Revised by:     Description:                This module implements the rate 1/2 tail biting convolutional                 encoder specified in section 8.4.9.2.1 of [1].References:                [1] IEEE P802.16-REVd/D5, May 2004******************************************************************************Target Processor:           ADSP-TS201Target Tools Revision:      easmts 1.6.0.11*****************************************************************************//*void cc_encoder_tailbiting_1_2(unsigned num_input_bytes,                               const uint4x8 *input_bytes,                               bit32x1 *output_bits)*/.section program;.global _cc_encoder_tailbiting_1_2;.align_code 4;_cc_encoder_tailbiting_1_2:// No preamble necessary because this is a leaf node and does// not use any reserved registers./////////////////////////////////////////////////////////////////// Setup section//  - Compute loop count//  - Set up circular buffer for input_bytes//  - Load input state//  - Loop entry code    // There are two major computions here:    //    //  1) Compute loop counter and circular buffer length.  This is mostly done    //     in the second column.    //     Loop counter = (num_input_bytes + 15)/16    //           (rounds num_input_bytes to nearest quadword)    //     circular buffer length = loop counter * 4    //    //  2) Get initial state.  This is mostly done in the first columne.    //     Since this is a tail biting encoder, this is taken from the end of     //     the input array.    //     //     The initial starting state will be     //     state = input_bytes[(num_input_bytes-1)/4] << (8*(3-(num_input_bytes-1)%4));    R0 = j4;               xR1 = 15;;    j9 = j4 - 1;           xR7 = 3;;    j0 = j5 + j31;         xR2 = R0 + R1;               R8 = 64;;    j10 = ASHIFTR j9;      xr6 = j9;;    j10 = ASHIFTR j10;     xR2 = LSHIFT R2 by -4;       R10 = 64;;    jB0 = j0 + j31;        xR3 = LSHIFT R2 by 2;        R9 = 64 - 2;;    xr6 = r7 AND r6;       j3  = xR2;;                           j8  = xR3;;    xr6 = r7 - r6;         lc0 = j3;                    R11 = 64 - 3;;                           jL0 = j8 + j31;;    xr6 = LSHIFT R6 by 3;  xR5 = [j5 + j10];;    // STALL    xr5 = LSHIFT r5 by r6;;    //  STALL (circular buffer)    //  Load in the first quadword of data.    xyR0 = CB [j0 += 1];;    xyR1 = CB [j0 += 1];;    xyR2 = CB [j0 += 1];;    xyR3 = CB [j0 += 1];;    // The main loop works on one quadword of input at a time.    // The first double word goes to XR3:2 and the second double word    // goes to YR3:2.    // However, both computations also need earlier bits for the     // encoder state.  This goes in the upper 6 bits of R1.    //   Y: State is already there from lower double word of input data    //   X: Load state from earlier data (or in first iteration,     //      from state input parameter.    xLR3:2 = PASS R1:0;  xR1:0 = LSHIFT R5:4 by 0;;    // STALL/////////////////////////////////////////////////////////////////// Main loop.// One iteration does the computation for 128 input bits..align_code 4;_MAIN_LOOP:    // X and Y each work on 64 bits at a time.    // The getbits commands implement the shift register.    // For example, the first getbits grabs the     // input delayed by 2.    R13:12 = getbits r3:0 by R9:8;   R9  = 64 - 6;;    R15:14 = getbits r3:0 by R11:10; R11 = 64 - 5;;    // R13:12 = 1 + D^2    LR13:12 = R3:2 xor R13:12;;    R17:16 = getbits r3:0 by R9:8;   R9  = 64 - 1;;    // R13:12 = 1 + D^2 + D^3    LR13:12 = R13:12 xor R15:14;;    R15:14 = getbits r3:0 by R11:10; R11 = 64 - 3;;     // R13:12 = 1 + D^2 + D^3 + D^6    // So far, this is common for both parity streams.    LR13:12 = R13:12 xor R17:16;;    R17:16 = getbits r3:0 by R9:8;   R9 = 64 - 2;;    // R13:12 = 1 + D + D^2 + D^3 + D^5 + D^6  = G1 parity stream    // R15:14 = 1 + D^2 + D^3 + D^5 + D^6      = G2 parity stream    // xR5 will be the state for the next loop iteration.    LR15:14 = R13:12 xor R15:14;     xR5:4 = yR3:2;;    LR13:12 = R13:12 xor R17:16;;    R13 = PASS R14;  R14 = R13;      xyR0 = CB [j0 += 1];;    // STALL        // Use the interleaved THR load to merge the G1 and G2 parity streams.    // In the background, load input data for the next iteration.    THR1:0 = R13:12 (I);                                  xyR1 = CB [j0 += 1];;    THR3:2 = R15:14 (I);   R13:12 = THR1:0;               xyR2 = CB [j0 += 1];;    R15:14 = THR3:2;                                      xyR3 = CB [j0 += 1];;    // Write output data.    // Note that this could be done quicker with quadword writes.    // However, since the rate 1/2 code is still much faster than the other ratesm    // we do it this way to avoid alignment restrictions.    [J6 += 1] = xR12;    xLR3:2 = PASS R1:0;;    [J6 += 1] = xR13;    xR1:0 = LSHIFT R5:4 by 0;;    [J6 += 1] = xR14;;    [J6 += 1] = xR15;;    [J6 += 1] = yR12;;    [J6 += 1] = yR13;;    [J6 += 1] = yR14;;    if nlc0e, JUMP _MAIN_LOOP;  [J6 += 1] = yR15;;    // Return to calling function    cjmp (ABS);     nop; nop; nop;;_cc_encoder_tailbiting_1_2.end: