/* File: CAN164.H */

/****************************************************************************
* 
* CAN164.100
* ==========
*
* TQ-Systems GmbH
* ----------------                                                         
* Costumer: TQC
* Project : STK16X, STK16XU 
* Module  : CAN
* Hardware: TQM167C, TQM164
* Tools   : uVision 2.10 with Keil C166 Compiler V4.10
* 
* Rev: Date:     Name:            Modification:
* ----+---------+----------------+------------------------------------------
* 100  18.09.98  F. Hattenhauer   initial version
*****************************************************************************/

/*--------------------------------------------------------------------------*
* number of CAN controller interrupt:
*---------------------------------------------------------------------------*/
#define XP0INT      0x40

/*--------------------------------------------------------------------------*
* CAN controller base address:
*---------------------------------------------------------------------------*/
#define CANBASIS  0xEF00

/*--------------------------------------------------------------------------*
* offset addresses of CAN controller and message buffer:
*---------------------------------------------------------------------------*/
#define MSGOFF      0x10
#define CAN_CTRL    0x00
#define CAN_MSG1    0x10
#define CAN_MSG2    0x20
#define CAN_MSG3    0x30
#define CAN_MSG4    0x40
#define CAN_MSG5    0x50
#define CAN_MSG6    0x60
#define CAN_MSG7    0x70
#define CAN_MSG8    0x80
#define CAN_MSG9    0x90
#define CAN_MSG10   0xA0
#define CAN_MSG11   0xB0
#define CAN_MSG12   0xC0
#define CAN_MSG13   0xD0
#define CAN_MSG14   0xE0
#define CAN_MSG15   0xF0

/*--------------------------------------------------------------------------*
* configuration register offsets:
*---------------------------------------------------------------------------*/
#define CAN_CR      0x00        /* control register   */
#define CAN_SR      0x01        /* Status Register    */
#define CAN_IR      0x02        /* interrupt register */
#define CAN_IPC     0x03        /* interface port control register */

#define CAN_BTR0    0x04        /* bus timing register 0 */
#define CAN_BTR1    0x05        /* bus timing Register 1 */

#define CAN_GMS0    0x06        /* global mask standard register 0 */
#define CAN_GMS1    0x07        /* global mask standard register 1 */

#define CAN_GML0    0x08        /* global mask long register 0     */
#define CAN_GML1    0x09        /* global mask long register 1     */
#define CAN_GML2    0x0A        /* global mask long register 2     */
#define CAN_GML3    0x0B        /* global mask long register 3     */

#define CAN_M15M0   0x0C        /* message 15 mask */
#define CAN_M15M1   0x0D        /* message 15 mask */
#define CAN_M15M2   0x0E        /* message 15 mask */
#define CAN_M15M3   0x0F        /* message 15 mask */

/*--------------------------------------------------------------------------*
* message object structure :
*---------------------------------------------------------------------------*/
#define CAN_MSG_CTR0    0x00    /* message control register 0 */
#define CAN_MSG_CTR1    0x01    /* message control register 1 */
#define CAN_MSG_AR0     0x02    /* arbitration register 0 */
#define CAN_MSG_AR1     0x03    /* arbitration register 1 */
#define CAN_MSG_AR2     0x04    /* arbitration register 2 */
#define CAN_MSG_AR3     0x05    /* arbitration register 3 */
#define CAN_MSG_CFR     0x06    /* message configuration register */
#define CAN_MSG_DATA1   0x07    /* data byte 0 */
#define CAN_MSG_DATA2   0x08    /* data byte 1 */
#define CAN_MSG_DATA3   0x09    /* data byte 2 */
#define CAN_MSG_DATA4   0x0A    /* data byte 3 */
#define CAN_MSG_DATA5   0x0B    /* data byte 4 */
#define CAN_MSG_DATA6   0x0C    /* data byte 5 */
#define CAN_MSG_DATA7   0x0D    /* data byte 6 */
#define CAN_MSG_DATA8   0x0E    /* data byte 7 */

/*--------------------------------------------------------------------------*
* C167 CAN interrupt control register:
*  bit 1,0 : group level  (3: highest, 0: lowest)
*  bit 5..2: interrupt priority level (0xF: highest, 0: lowest)
*  bit 6   : interrupt enable
*  bit 7   : interrupt request flag
*---------------------------------------------------------------------------*/
#define I_XP0IC         0x5D    /* 0101.1101 */

/*--------------------------------------------------------------------------*
* CAN controller settings:
*---------------------------------------------------------------------------*/
#define I_CAN_CR        0x02    /* interrupt enable (0000.0010)          */
#define I_CAN_SR        0x07    /* reset TXOK, RXOK; last error code = 7 */
#define I_CAN_IPC       0x00    /* IPC = 000b  --> CAN1/CAN2 = P4.4..P4.7*/

#define I_CAN_BTR0_50   0xD3    /* bit timing register 0        */ 
#define I_CAN_BTR0_125  0xC7
#define I_CAN_BTR0_250  0xC3
#define I_CAN_BTR0_500  0xC1
#define I_CAN_BTR1      0x34    /* bit timing register 1        */ 

#define I_CAN_GMS0      0xFF    /* global mask register         */
#define I_CAN_GMS1      0xFF
#define I_CAN_GML0      0xFF
#define I_CAN_GML1      0xFF
#define I_CAN_GML2      0xFF
#define I_CAN_GML3      0xFF
#define I_CAN_M15M0     0xFF
#define I_CAN_M15M1     0xFF
#define I_CAN_M15M2     0xFF
#define I_CAN_M15M3     0xFF

/*--------------------------------------------------------------------------*
* message control register (init values for WRITE):
*  DLC: 8 (message length)
*  DIR: 1 (message direction = transmit)
*  XTD: 0 (11 bit tdentifier)
*---------------------------------------------------------------------------*/
#define IW_CAN_MSG_CFR  0x88
#define IW_CAN_MSG_CTR0 0xBF    /* MCR0: message valid, no transmit IRQ    */
#define IW_CAN_MSG_CTR1 0xFF    /* MCR0: no change of default init values  */

/*--------------------------------------------------------------------------*
* message control register (init values for READ):
*  DLC: 8 Alle MMM-Messages haben die Laenge
*  DIR: 0 Message Direction receive
*  XTD: 0 11Bit Identifier
*---------------------------------------------------------------------------*/
#define IR_CAN_MSG_CFR  0x80
#define IR_CAN_MSG_CTR0 0xBB    /* MCR0: message valid, enable receive IRQ */
#define IR_CAN_MSG_CTR1 0xFF    /* MCR1: no change of default init values  */